Annotation of sys/arch/alpha/pci/apecs_bus_io.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: apecs_bus_io.c,v 1.6 2001/11/06 19:53:13 miod Exp $ */
2: /* $NetBSD: apecs_bus_io.c,v 1.8 1997/09/02 13:19:10 thorpej Exp $ */
3:
4: /*
5: * Copyright (c) 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: #include <sys/param.h>
32: #include <sys/systm.h>
33: #include <sys/malloc.h>
34: #include <sys/syslog.h>
35: #include <sys/device.h>
36:
37: #include <uvm/uvm_extern.h>
38:
39: #include <machine/bus.h>
40:
41: #include <alpha/pci/apecsreg.h>
42: #include <alpha/pci/apecsvar.h>
43:
44: #define CHIP apecs
45:
46: #define CHIP_EX_MALLOC_SAFE(v) (((struct apecs_config *)(v))->ac_mallocsafe)
47: #define CHIP_IO_EXTENT(v) (((struct apecs_config *)(v))->ac_io_ex)
48:
49: /* IO region 1 */
50: #define CHIP_IO_W1_BUS_START(v) 0x00000000UL
51: #define CHIP_IO_W1_BUS_END(v) 0x0003ffffUL
52: #define CHIP_IO_W1_SYS_START(v) APECS_PCI_SIO
53: #define CHIP_IO_W1_SYS_END(v) (APECS_PCI_SIO + (0x00040000UL << 5) - 1)
54:
55: /* IO region 2 */
56: #define CHIP_IO_W2_BUS_START(v) \
57: ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \
58: 0x00040000UL)
59: #define CHIP_IO_W2_BUS_END(v) \
60: ((((struct apecs_config *)(v))->ac_haxr2 & EPIC_HAXR2_EADDR) + \
61: 0x00ffffffUL)
62: #define CHIP_IO_W2_SYS_START(v) (APECS_PCI_SIO + (0x00040000UL << 5))
63: #define CHIP_IO_W2_SYS_END(v) (APECS_PCI_SIO + (0x01000000UL << 5) - 1)
64:
65: #include <alpha/pci/pci_swiz_bus_io_chipdep.c>
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