Annotation of sys/arch/alpha/pci/cia_bus_mem.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: cia_bus_mem.c,v 1.8 2001/11/06 19:53:13 miod Exp $ */
2: /* $NetBSD: cia_bus_mem.c,v 1.7 1996/11/25 03:46:09 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1996 Carnegie-Mellon University.
6: * All rights reserved.
7: *
8: * Author: Chris G. Demetriou
9: *
10: * Permission to use, copy, modify and distribute this software and
11: * its documentation is hereby granted, provided that both the copyright
12: * notice and this permission notice appear in all copies of the
13: * software, derivative works or modified versions, and any portions
14: * thereof, and that both notices appear in supporting documentation.
15: *
16: * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
17: * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
18: * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
19: *
20: * Carnegie Mellon requests users of this software to return to
21: *
22: * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
23: * School of Computer Science
24: * Carnegie Mellon University
25: * Pittsburgh PA 15213-3890
26: *
27: * any improvements or extensions that they make and grant Carnegie the
28: * rights to redistribute these changes.
29: */
30:
31: #include <sys/param.h>
32: #include <sys/systm.h>
33: #include <sys/malloc.h>
34: #include <sys/syslog.h>
35: #include <sys/device.h>
36: #include <uvm/uvm_extern.h>
37:
38: #include <machine/bus.h>
39:
40: #include <alpha/pci/ciareg.h>
41: #include <alpha/pci/ciavar.h>
42:
43: #define CHIP cia
44:
45: #define CHIP_EX_MALLOC_SAFE(v) (((struct cia_config *)(v))->cc_mallocsafe)
46: #define CHIP_D_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_d_mem_ex)
47: #define CHIP_S_MEM_EXTENT(v) (((struct cia_config *)(v))->cc_s_mem_ex)
48:
49: /* Dense region 1 */
50: #define CHIP_D_MEM_W1_BUS_START(v) 0x00000000UL
51: #define CHIP_D_MEM_W1_BUS_END(v) 0xffffffffUL
52: #define CHIP_D_MEM_W1_SYS_START(v) CIA_PCI_DENSE
53: #define CHIP_D_MEM_W1_SYS_END(v) (CIA_PCI_DENSE + 0xffffffffUL)
54:
55: /* Sparse region 1 */
56: #define CHIP_S_MEM_W1_BUS_START(v) \
57: HAE_MEM_REG1_START(((struct cia_config *)(v))->cc_hae_mem)
58: #define CHIP_S_MEM_W1_BUS_END(v) \
59: (CHIP_S_MEM_W1_BUS_START(v) + HAE_MEM_REG1_MASK)
60: #define CHIP_S_MEM_W1_SYS_START(v) \
61: CIA_PCI_SMEM1
62: #define CHIP_S_MEM_W1_SYS_END(v) \
63: (CIA_PCI_SMEM1 + ((HAE_MEM_REG1_MASK + 1) << 5) - 1)
64:
65: /* Sparse region 2 */
66: #define CHIP_S_MEM_W2_BUS_START(v) \
67: HAE_MEM_REG2_START(((struct cia_config *)(v))->cc_hae_mem)
68: #define CHIP_S_MEM_W2_BUS_END(v) \
69: (CHIP_S_MEM_W2_BUS_START(v) + HAE_MEM_REG2_MASK)
70: #define CHIP_S_MEM_W2_SYS_START(v) \
71: CIA_PCI_SMEM2
72: #define CHIP_S_MEM_W2_SYS_END(v) \
73: (CIA_PCI_SMEM2 + ((HAE_MEM_REG2_MASK + 1) << 5) - 1)
74:
75: /* Sparse region 3 */
76: #define CHIP_S_MEM_W3_BUS_START(v) \
77: HAE_MEM_REG3_START(((struct cia_config *)(v))->cc_hae_mem)
78: #define CHIP_S_MEM_W3_BUS_END(v) \
79: (CHIP_S_MEM_W3_BUS_START(v) + HAE_MEM_REG3_MASK)
80: #define CHIP_S_MEM_W3_SYS_START(v) \
81: CIA_PCI_SMEM3
82: #define CHIP_S_MEM_W3_SYS_END(v) \
83: (CIA_PCI_SMEM3 + ((HAE_MEM_REG3_MASK + 1) << 5) - 1)
84:
85: #include "pci_swiz_bus_mem_chipdep.c"
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