Annotation of sys/arch/alpha/pci/sioreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: sioreg.h,v 1.3 1996/10/30 22:40:16 niklas Exp $ */
2: /* $NetBSD: sioreg.h,v 1.1 1996/04/23 14:10:53 cgd Exp $ */
3:
4: /*
5: * Copyright (c) 1996 BBN Corporation.
6: * BBN Systems and Technologies Division
7: * 10 Moulton Street
8: * Cambridge, Ma. 02138
9: * 617-873-3000
10: *
11: * Permission to use, copy, modify, distribute, and sell this software and its
12: * documentation for any purpose is hereby granted without fee, provided that
13: * the above copyright notice and this permission appear in all copies and in
14: * supporting documentation, and that the name of BBN Corporation not be used
15: * in advertising or publicity pertaining to distribution of the software
16: * without specific, written prior permission. BBN makes no representations
17: * about the suitability of this software for any purposes. It is provided
18: * "AS IS" without express or implied warranties.
19: */
20:
21: /*
22: * Intel 82378 System I/O (SIO) Chip
23: *
24: * Taken from the Intel "Peripheral Components" manual, 1995 Edition.
25: */
26:
27:
28: /*
29: * Device-specific PCI Configuration Registers
30: */
31:
32: /*
33: * PCI Control Registers
34: */
35: #define SIO_PCIREG_PCICON 0x40 /* PCI Control */
36: #define SIO_PCIREG_PAC 0x41 /* PCI Arbiter Control */
37: #define SIO_PCIREG_PAPC 0x42 /* PCI Arbiter Priority Control */
38: #define SIO_PCIREG_ARBPRIX 0x43 /* PCI Arbiter Priority Control Ext. */
39:
40: /*
41: * Memory Chip Select Registers
42: */
43: #define SIO_PCIREG_MEMCSCON 0x44 /* MEMCS# Control */
44: #define SIO_PCIREG_MEMCSBOH 0x45 /* MEMCS# Bottom of Hole */
45: #define SIO_PCIREG_MEMCSTOH 0x46 /* MEMCS# Top of Hole */
46: #define SIO_PCIREG_MEMCSTOM 0x47 /* MEMCS# Top of Memory */
47:
48: #define SIO_PCIREG_MAR1 0x54 /* MEMCS# Attribute 1 */
49: #define SIO_PCIREG_MAR2 0x55 /* MEMCS# Attribute 2 */
50: #define SIO_PCIREG_MAR3 0x56 /* MEMCS# Attribute 3 */
51: #define SIO_PCIREG_DMASGRB 0x57 /* DMA Scatter/Gather Rel. Base Addr. */
52:
53: /*
54: * ISA Address Decoder Registers
55: */
56: #define SIO_PCIREG_IADCON 0x48 /* ISA Address Decoder Control */
57: #define SIO_PCIREG_IADRBE 0x49 /* ISA Addr. Decoder ROM Block Enable */
58: #define SIO_PCIREG_IADBOH 0x4A /* ISA Addr. Decoder Bottom of Hole */
59: #define SIO_PCIREG_IADTOH 0x4B /* ISA Addr. Decoder Top of Hole */
60:
61: /*
62: * Clocks and Timers
63: */
64: #define SIO_PCIREG_ICRT 0x4C /* ISA Controller Recovery Timer */
65: #define SIO_PCIREG_ICD 0x4D /* ISA Clock Divisor */
66:
67: #define SIO_PCIREG_ 0x80 /* BIOS Timer Base Address */
68:
69: #define SIO_PCIREG_CTLTMRL 0xAC /* Clock Throttle STPCLK# Low Timer */
70: #define SIO_PCIREG_CTLTMRH 0xAE /* Clock Throttle STPCLK# High Timer */
71:
72: /*
73: * Miscellaneous
74: */
75: #define SIO_PCIREG_UBCSA 0x4E /* Utility Bus Chip Select A */
76: #define SIO_PCIREG_UBCSB 0x4F /* Utility Bus Chip Select B */
77:
78: /*
79: * PIRQ# Route Control
80: */
81: #define SIO_PCIREG_PIRQ0 0x60 /* PIRQ0 Route Control */
82: #define SIO_PCIREG_PIRQ1 0x61 /* PIRQ1 Route Control */
83: #define SIO_PCIREG_PIRQ2 0x62 /* PIRQ2 Route Control */
84: #define SIO_PCIREG_PIRQ3 0x63 /* PIRQ3 Route Control */
85: #define SIO_PCIREG_PIRQ_RTCTRL SIO_PCIREG_PIRQ0
86:
87: /*
88: * System Management Interrupt (SMI)
89: */
90: #define SIO_PCIREG_SMICNTL 0xA0 /* SMI Control */
91: #define SIO_PCIREG_SMIEN 0xA2 /* SMI Enable */
92: #define SIO_PCIREG_SEE 0xA4 /* System Event Enable */
93: #define SIO_PCIREG_FTMR 0xA8 /* Fast Off Timer */
94: #define SIO_PCIREG_SMIREQ 0xAA /* SMI Request */
95:
96:
97: /*
98: * Non-Configuration Registers
99: */
100:
101: /*
102: * Control
103: */
104: #define SIO_REG_RSTUB 0x060 /* Reset UBus */
105: #define SIO_REG_NMICTRL 0x061 /* NMI Status and Control */
106: #define SIO_REG_CMOSRAM 0x070 /* CMOS RAM Address and NMI Mask */
107: #define SIO_REG_NMIMASK 0x070 /* CMOS RAM Address and NMI Mask */
108: #define SIO_REG_PORT92 0x092 /* Port 92 */
109: #define SIO_REG_CPERR 0x0F0 /* Coprocessor Error */
110:
111: /*
112: * Interrupt
113: */
114: #define SIO_REG_ICU1 0x020 /* Intr. Controller #1 Control */
115: #define SIO_REG_ICU1MASK 0x021 /* Intr. Controller #1 Mask */
116: #define SIO_REG_ICU2 0x0A0 /* Intr. Controller #2 Control */
117: #define SIO_REG_ICU2MASK 0x0A1 /* Intr. Controller #2 Mask */
118: #define SIO_REG_ICU1ELC 0x4D0 /* #1's Edge/Level Control */
119: #define SIO_REG_ICU2ELC 0x4D1 /* #2's Edge/Level Control */
120: #define SIO_ICUSIZE 16 /* I/O Port Sizes */
121:
122: /*
123: * Timer
124: */
125: /* XXX need Timer definitions */
126:
127: /*
128: * DMA
129: */
130: /* XXX need DMA definitions */
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