Annotation of sys/arch/amd64/include/specialreg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: specialreg.h,v 1.11 2007/06/01 22:28:21 tedu Exp $ */
! 2: /* $NetBSD: specialreg.h,v 1.1 2003/04/26 18:39:48 fvdl Exp $ */
! 3: /* $NetBSD: x86/specialreg.h,v 1.2 2003/04/25 21:54:30 fvdl Exp $ */
! 4:
! 5: /*-
! 6: * Copyright (c) 1991 The Regents of the University of California.
! 7: * All rights reserved.
! 8: *
! 9: * Redistribution and use in source and binary forms, with or without
! 10: * modification, are permitted provided that the following conditions
! 11: * are met:
! 12: * 1. Redistributions of source code must retain the above copyright
! 13: * notice, this list of conditions and the following disclaimer.
! 14: * 2. Redistributions in binary form must reproduce the above copyright
! 15: * notice, this list of conditions and the following disclaimer in the
! 16: * documentation and/or other materials provided with the distribution.
! 17: * 3. Neither the name of the University nor the names of its contributors
! 18: * may be used to endorse or promote products derived from this software
! 19: * without specific prior written permission.
! 20: *
! 21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 31: * SUCH DAMAGE.
! 32: *
! 33: * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
! 34: */
! 35:
! 36: /*
! 37: * Bits in 386 special registers:
! 38: */
! 39: #define CR0_PE 0x00000001 /* Protected mode Enable */
! 40: #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
! 41: #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
! 42: #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
! 43: #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
! 44: #define CR0_PG 0x80000000 /* PaGing enable */
! 45:
! 46: /*
! 47: * Bits in 486 special registers:
! 48: */
! 49: #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
! 50: #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
! 51: #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
! 52: #define CR0_NW 0x20000000 /* Not Write-through */
! 53: #define CR0_CD 0x40000000 /* Cache Disable */
! 54:
! 55: /*
! 56: * Cyrix 486 DLC special registers, accessible as IO ports.
! 57: */
! 58: #define CCR0 0xc0 /* configuration control register 0 */
! 59: #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
! 60: #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
! 61: #define CCR0_A20M 0x04 /* enables A20M# input pin */
! 62: #define CCR0_KEN 0x08 /* enables KEN# input pin */
! 63: #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
! 64: #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
! 65: #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
! 66: #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
! 67:
! 68: #define CCR1 0xc1 /* configuration control register 1 */
! 69: #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
! 70: /* the remaining 7 bits of this register are reserved */
! 71:
! 72: /*
! 73: * bits in the pentiums %cr4 register:
! 74: */
! 75:
! 76: #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
! 77: #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
! 78: #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
! 79: #define CR4_DE 0x00000008 /* debugging extension */
! 80: #define CR4_PSE 0x00000010 /* large (4MB) page size enable */
! 81: #define CR4_PAE 0x00000020 /* physical address extension enable */
! 82: #define CR4_MCE 0x00000040 /* machine check enable */
! 83: #define CR4_PGE 0x00000080 /* page global enable */
! 84: #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
! 85: #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
! 86: #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
! 87:
! 88: /*
! 89: * CPUID "features" bits:
! 90: */
! 91:
! 92: #define CPUID_FPU 0x00000001 /* processor has an FPU? */
! 93: #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
! 94: #define CPUID_DE 0x00000004 /* has debugging extension */
! 95: #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
! 96: #define CPUID_TSC 0x00000010 /* has time stamp counter */
! 97: #define CPUID_MSR 0x00000020 /* has mode specific registers */
! 98: #define CPUID_PAE 0x00000040 /* has phys address extension */
! 99: #define CPUID_MCE 0x00000080 /* has machine check exception */
! 100: #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
! 101: #define CPUID_APIC 0x00000200 /* has enabled APIC */
! 102: #define CPUID_B10 0x00000400 /* reserved, MTRR */
! 103: #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
! 104: #define CPUID_MTRR 0x00001000 /* has memory type range register */
! 105: #define CPUID_PGE 0x00002000 /* has page global extension */
! 106: #define CPUID_MCA 0x00004000 /* has machine check architecture */
! 107: #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
! 108: #define CPUID_PAT 0x00010000 /* Page Attribute Table */
! 109: #define CPUID_PSE36 0x00020000 /* 36-bit PSE */
! 110: #define CPUID_PN 0x00040000 /* processor serial number */
! 111: #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
! 112: #define CPUID_B20 0x00100000 /* reserved */
! 113: #define CPUID_DS 0x00200000 /* Debug Store */
! 114: #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
! 115: #define CPUID_MMX 0x00800000 /* MMX supported */
! 116: #define CPUID_FXSR 0x01000000 /* FP/MMX save/restore */
! 117: #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
! 118: #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
! 119: #define CPUID_SS 0x08000000 /* self-snoop */
! 120: #define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
! 121: #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
! 122: #define CPUID_B30 0x40000000 /* reserved */
! 123: #define CPUID_SBF 0x80000000 /* signal break on FERR */
! 124:
! 125: #define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */
! 126: #define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */
! 127: #define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */
! 128: #define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */
! 129: #define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */
! 130: #define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */
! 131: #define CPUIDECX_CNXTID 0x00000400 /* Context ID */
! 132: #define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */
! 133: #define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */
! 134:
! 135: /*
! 136: * AMD/VIA processor specific flags.
! 137: */
! 138:
! 139: #define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
! 140: #define CPUID_NXE 0x00100000 /* No-Execute Extension */
! 141: #define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
! 142: #define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */
! 143: #define CPUID_LONG 0x20000000 /* long mode */
! 144: #define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
! 145: #define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
! 146:
! 147: #define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15)
! 148: #define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15)
! 149: #define CPUID2STEPPING(cpuid) ((cpuid) & 15)
! 150:
! 151: #define CPUID(code, eax, ebx, ecx, edx) \
! 152: __asm("cpuid" \
! 153: : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
! 154: : "a" (code));
! 155:
! 156:
! 157: /*
! 158: * Model-specific registers for the i386 family
! 159: */
! 160: #define MSR_P5_MC_ADDR 0x000 /* P5 only */
! 161: #define MSR_P5_MC_TYPE 0x001 /* P5 only */
! 162: #define MSR_TSC 0x010
! 163: #define MSR_CESR 0x011 /* P5 only (trap on P6) */
! 164: #define MSR_CTR0 0x012 /* P5 only (trap on P6) */
! 165: #define MSR_CTR1 0x013 /* P5 only (trap on P6) */
! 166: #define MSR_APICBASE 0x01b
! 167: #define MSR_EBL_CR_POWERON 0x02a
! 168: #define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */
! 169: #define MSR_TEST_CTL 0x033
! 170: #define MSR_BIOS_UPDT_TRIG 0x079
! 171: #define MSR_BBL_CR_D0 0x088 /* PII+ only */
! 172: #define MSR_BBL_CR_D1 0x089 /* PII+ only */
! 173: #define MSR_BBL_CR_D2 0x08a /* PII+ only */
! 174: #define MSR_BIOS_SIGN 0x08b
! 175: #define MSR_PERFCTR0 0x0c1
! 176: #define MSR_PERFCTR1 0x0c2
! 177: #define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
! 178: /* not documented anywhere, see intelcore_update_sensor() */
! 179: #define MSR_TEMPERATURE_TARGET 0x0ee
! 180: #define MSR_TEMPERATURE_TARGET_LOW_BIT 0x40000000
! 181: #define MSR_MTRRcap 0x0fe
! 182: #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
! 183: #define MSR_BBL_CR_DECC 0x118 /* PII+ only */
! 184: #define MSR_BBL_CR_CTL 0x119 /* PII+ only */
! 185: #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
! 186: #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
! 187: #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
! 188: #define MSR_SYSENTER_CS 0x174 /* PII+ only */
! 189: #define MSR_SYSENTER_ESP 0x175 /* PII+ only */
! 190: #define MSR_SYSENTER_EIP 0x176 /* PII+ only */
! 191: #define MSR_MCG_CAP 0x179
! 192: #define MSR_MCG_STATUS 0x17a
! 193: #define MSR_MCG_CTL 0x17b
! 194: #define MSR_EVNTSEL0 0x186
! 195: #define MSR_EVNTSEL1 0x187
! 196: #define MSR_PERF_STATUS 0x198 /* Pentium M */
! 197: #define MSR_PERF_CTL 0x199 /* Pentium M */
! 198: #define MSR_THERM_CONTROL 0x19a
! 199: #define MSR_THERM_INTERRUPT 0x19b
! 200: #define MSR_THERM_STATUS 0x19c
! 201: #define MSR_THERM_STATUS_VALID_BIT 0x80000000
! 202: #define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f)
! 203: #define MSR_THERM2_CTL 0x19d /* Pentium M */
! 204: #define MSR_DEBUGCTLMSR 0x1d9
! 205: #define MSR_LASTBRANCHFROMIP 0x1db
! 206: #define MSR_LASTBRANCHTOIP 0x1dc
! 207: #define MSR_LASTINTFROMIP 0x1dd
! 208: #define MSR_LASTINTTOIP 0x1de
! 209: #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
! 210: #define MSR_MTRRphysBase0 0x200
! 211: #define MSR_MTRRphysMask0 0x201
! 212: #define MSR_MTRRphysBase1 0x202
! 213: #define MSR_MTRRphysMask1 0x203
! 214: #define MSR_MTRRphysBase2 0x204
! 215: #define MSR_MTRRphysMask2 0x205
! 216: #define MSR_MTRRphysBase3 0x206
! 217: #define MSR_MTRRphysMask3 0x207
! 218: #define MSR_MTRRphysBase4 0x208
! 219: #define MSR_MTRRphysMask4 0x209
! 220: #define MSR_MTRRphysBase5 0x20a
! 221: #define MSR_MTRRphysMask5 0x20b
! 222: #define MSR_MTRRphysBase6 0x20c
! 223: #define MSR_MTRRphysMask6 0x20d
! 224: #define MSR_MTRRphysBase7 0x20e
! 225: #define MSR_MTRRphysMask7 0x20f
! 226: #define MSR_MTRRfix64K_00000 0x250
! 227: #define MSR_MTRRfix16K_80000 0x258
! 228: #define MSR_MTRRfix16K_A0000 0x259
! 229: #define MSR_MTRRfix4K_C0000 0x268
! 230: #define MSR_MTRRfix4K_C8000 0x269
! 231: #define MSR_MTRRfix4K_D0000 0x26a
! 232: #define MSR_MTRRfix4K_D8000 0x26b
! 233: #define MSR_MTRRfix4K_E0000 0x26c
! 234: #define MSR_MTRRfix4K_E8000 0x26d
! 235: #define MSR_MTRRfix4K_F0000 0x26e
! 236: #define MSR_MTRRfix4K_F8000 0x26f
! 237: #define MSR_MTRRdefType 0x2ff
! 238: #define MSR_MC0_CTL 0x400
! 239: #define MSR_MC0_STATUS 0x401
! 240: #define MSR_MC0_ADDR 0x402
! 241: #define MSR_MC0_MISC 0x403
! 242: #define MSR_MC1_CTL 0x404
! 243: #define MSR_MC1_STATUS 0x405
! 244: #define MSR_MC1_ADDR 0x406
! 245: #define MSR_MC1_MISC 0x407
! 246: #define MSR_MC2_CTL 0x408
! 247: #define MSR_MC2_STATUS 0x409
! 248: #define MSR_MC2_ADDR 0x40a
! 249: #define MSR_MC2_MISC 0x40b
! 250: #define MSR_MC4_CTL 0x40c
! 251: #define MSR_MC4_STATUS 0x40d
! 252: #define MSR_MC4_ADDR 0x40e
! 253: #define MSR_MC4_MISC 0x40f
! 254: #define MSR_MC3_CTL 0x410
! 255: #define MSR_MC3_STATUS 0x411
! 256: #define MSR_MC3_ADDR 0x412
! 257: #define MSR_MC3_MISC 0x413
! 258:
! 259: /*
! 260: * AMD K6/K7 MSRs.
! 261: */
! 262: #define MSR_K6_UWCCR 0xc0000085
! 263: #define MSR_K7_EVNTSEL0 0xc0010000
! 264: #define MSR_K7_EVNTSEL1 0xc0010001
! 265: #define MSR_K7_EVNTSEL2 0xc0010002
! 266: #define MSR_K7_EVNTSEL3 0xc0010003
! 267: #define MSR_K7_PERFCTR0 0xc0010004
! 268: #define MSR_K7_PERFCTR1 0xc0010005
! 269: #define MSR_K7_PERFCTR2 0xc0010006
! 270: #define MSR_K7_PERFCTR3 0xc0010007
! 271:
! 272: /*
! 273: * AMD K8 (Opteron) MSRs.
! 274: */
! 275: #define MSR_SYSCFG 0xc0000010
! 276:
! 277: #define MSR_EFER 0xc0000080 /* Extended feature enable */
! 278: #define EFER_SCE 0x00000001 /* SYSCALL extension */
! 279: #define EFER_LME 0x00000100 /* Long Mode Active */
! 280: #define EFER_LMA 0x00000400 /* Long Mode Enabled */
! 281: #define EFER_NXE 0x00000800 /* No-Execute Enabled */
! 282:
! 283: #define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
! 284: #define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
! 285: #define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
! 286: #define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
! 287:
! 288: #define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
! 289: #define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
! 290: #define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
! 291:
! 292: /*
! 293: * These require a 'passcode' for access. See cpufunc.h.
! 294: */
! 295: #define MSR_HWCR 0xc0010015
! 296: #define HWCR_FFDIS 0x00000040
! 297:
! 298: #define MSR_NB_CFG 0xc001001f
! 299: #define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL
! 300: #define NB_CFG_DISDATMSK 0x0000001000000000ULL
! 301:
! 302: #define MSR_LS_CFG 0xc0011020
! 303: #define LS_CFG_DIS_LS2_SQUISH 0x02000000
! 304:
! 305: #define MSR_IC_CFG 0xc0011021
! 306: #define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
! 307:
! 308: #define MSR_DC_CFG 0xc0011022
! 309: #define DC_CFG_DIS_CNV_WC_SSO 0x00000004
! 310: #define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
! 311:
! 312: #define MSR_BU_CFG 0xc0011023
! 313: #define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
! 314: #define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
! 315: #define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
! 316:
! 317: /*
! 318: * Constants related to MTRRs
! 319: */
! 320: #define MTRR_N64K 8 /* numbers of fixed-size entries */
! 321: #define MTRR_N16K 16
! 322: #define MTRR_N4K 64
! 323:
! 324: /*
! 325: * the following four 3-byte registers control the non-cacheable regions.
! 326: * These registers must be written as three separate bytes.
! 327: *
! 328: * NCRx+0: A31-A24 of starting address
! 329: * NCRx+1: A23-A16 of starting address
! 330: * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
! 331: *
! 332: * The non-cacheable region's starting address must be aligned to the
! 333: * size indicated by the NCR_SIZE_xx field.
! 334: */
! 335: #define NCR1 0xc4
! 336: #define NCR2 0xc7
! 337: #define NCR3 0xca
! 338: #define NCR4 0xcd
! 339:
! 340: #define NCR_SIZE_0K 0
! 341: #define NCR_SIZE_4K 1
! 342: #define NCR_SIZE_8K 2
! 343: #define NCR_SIZE_16K 3
! 344: #define NCR_SIZE_32K 4
! 345: #define NCR_SIZE_64K 5
! 346: #define NCR_SIZE_128K 6
! 347: #define NCR_SIZE_256K 7
! 348: #define NCR_SIZE_512K 8
! 349: #define NCR_SIZE_1M 9
! 350: #define NCR_SIZE_2M 10
! 351: #define NCR_SIZE_4M 11
! 352: #define NCR_SIZE_8M 12
! 353: #define NCR_SIZE_16M 13
! 354: #define NCR_SIZE_32M 14
! 355: #define NCR_SIZE_4G 15
! 356:
! 357: /*
! 358: * Performance monitor events.
! 359: *
! 360: * Note that 586-class and 686-class CPUs have different performance
! 361: * monitors available, and they are accessed differently:
! 362: *
! 363: * 686-class: `rdpmc' instruction
! 364: * 586-class: `rdmsr' instruction, CESR MSR
! 365: *
! 366: * The descriptions of these events are too lenghy to include here.
! 367: * See Appendix A of "Intel Architecture Software Developer's
! 368: * Manual, Volume 3: System Programming" for more information.
! 369: */
! 370:
! 371: /*
! 372: * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
! 373: * is CTR1.
! 374: */
! 375:
! 376: #define PMC5_CESR_EVENT 0x003f
! 377: #define PMC5_CESR_OS 0x0040
! 378: #define PMC5_CESR_USR 0x0080
! 379: #define PMC5_CESR_E 0x0100
! 380: #define PMC5_CESR_P 0x0200
! 381:
! 382: #define PMC5_DATA_READ 0x00
! 383: #define PMC5_DATA_WRITE 0x01
! 384: #define PMC5_DATA_TLB_MISS 0x02
! 385: #define PMC5_DATA_READ_MISS 0x03
! 386: #define PMC5_DATA_WRITE_MISS 0x04
! 387: #define PMC5_WRITE_M_E 0x05
! 388: #define PMC5_DATA_LINES_WBACK 0x06
! 389: #define PMC5_DATA_CACHE_SNOOP 0x07
! 390: #define PMC5_DATA_CACHE_SNOOP_HIT 0x08
! 391: #define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
! 392: #define PMC5_BANK_CONFLICTS 0x0a
! 393: #define PMC5_MISALIGNED_DATA 0x0b
! 394: #define PMC5_INST_READ 0x0c
! 395: #define PMC5_INST_TLB_MISS 0x0d
! 396: #define PMC5_INST_CACHE_MISS 0x0e
! 397: #define PMC5_SEGMENT_REG_LOAD 0x0f
! 398: #define PMC5_BRANCHES 0x12
! 399: #define PMC5_BTB_HITS 0x13
! 400: #define PMC5_BRANCH_TAKEN 0x14
! 401: #define PMC5_PIPELINE_FLUSH 0x15
! 402: #define PMC5_INST_EXECUTED 0x16
! 403: #define PMC5_INST_EXECUTED_V_PIPE 0x17
! 404: #define PMC5_BUS_UTILIZATION 0x18
! 405: #define PMC5_WRITE_BACKUP_STALL 0x19
! 406: #define PMC5_DATA_READ_STALL 0x1a
! 407: #define PMC5_WRITE_E_M_STALL 0x1b
! 408: #define PMC5_LOCKED_BUS 0x1c
! 409: #define PMC5_IO_CYCLE 0x1d
! 410: #define PMC5_NONCACHE_MEM_READ 0x1e
! 411: #define PMC5_AGI_STALL 0x1f
! 412: #define PMC5_FLOPS 0x22
! 413: #define PMC5_BP0_MATCH 0x23
! 414: #define PMC5_BP1_MATCH 0x24
! 415: #define PMC5_BP2_MATCH 0x25
! 416: #define PMC5_BP3_MATCH 0x26
! 417: #define PMC5_HARDWARE_INTR 0x27
! 418: #define PMC5_DATA_RW 0x28
! 419: #define PMC5_DATA_RW_MISS 0x29
! 420:
! 421: /*
! 422: * 686-class Event Selector MSR format.
! 423: */
! 424:
! 425: #define PMC6_EVTSEL_EVENT 0x000000ff
! 426: #define PMC6_EVTSEL_UNIT 0x0000ff00
! 427: #define PMC6_EVTSEL_UNIT_SHIFT 8
! 428: #define PMC6_EVTSEL_USR (1 << 16)
! 429: #define PMC6_EVTSEL_OS (1 << 17)
! 430: #define PMC6_EVTSEL_E (1 << 18)
! 431: #define PMC6_EVTSEL_PC (1 << 19)
! 432: #define PMC6_EVTSEL_INT (1 << 20)
! 433: #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
! 434: #define PMC6_EVTSEL_INV (1 << 23)
! 435: #define PMC6_EVTSEL_COUNTER_MASK 0xff000000
! 436: #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
! 437:
! 438: /* Data Cache Unit */
! 439: #define PMC6_DATA_MEM_REFS 0x43
! 440: #define PMC6_DCU_LINES_IN 0x45
! 441: #define PMC6_DCU_M_LINES_IN 0x46
! 442: #define PMC6_DCU_M_LINES_OUT 0x47
! 443: #define PMC6_DCU_MISS_OUTSTANDING 0x48
! 444:
! 445: /* Instruction Fetch Unit */
! 446: #define PMC6_IFU_IFETCH 0x80
! 447: #define PMC6_IFU_IFETCH_MISS 0x81
! 448: #define PMC6_ITLB_MISS 0x85
! 449: #define PMC6_IFU_MEM_STALL 0x86
! 450: #define PMC6_ILD_STALL 0x87
! 451:
! 452: /* L2 Cache */
! 453: #define PMC6_L2_IFETCH 0x28
! 454: #define PMC6_L2_LD 0x29
! 455: #define PMC6_L2_ST 0x2a
! 456: #define PMC6_L2_LINES_IN 0x24
! 457: #define PMC6_L2_LINES_OUT 0x26
! 458: #define PMC6_L2_M_LINES_INM 0x25
! 459: #define PMC6_L2_M_LINES_OUTM 0x27
! 460: #define PMC6_L2_RQSTS 0x2e
! 461: #define PMC6_L2_ADS 0x21
! 462: #define PMC6_L2_DBUS_BUSY 0x22
! 463: #define PMC6_L2_DBUS_BUSY_RD 0x23
! 464:
! 465: /* External Bus Logic */
! 466: #define PMC6_BUS_DRDY_CLOCKS 0x62
! 467: #define PMC6_BUS_LOCK_CLOCKS 0x63
! 468: #define PMC6_BUS_REQ_OUTSTANDING 0x60
! 469: #define PMC6_BUS_TRAN_BRD 0x65
! 470: #define PMC6_BUS_TRAN_RFO 0x66
! 471: #define PMC6_BUS_TRANS_WB 0x67
! 472: #define PMC6_BUS_TRAN_IFETCH 0x68
! 473: #define PMC6_BUS_TRAN_INVAL 0x69
! 474: #define PMC6_BUS_TRAN_PWR 0x6a
! 475: #define PMC6_BUS_TRANS_P 0x6b
! 476: #define PMC6_BUS_TRANS_IO 0x6c
! 477: #define PMC6_BUS_TRAN_DEF 0x6d
! 478: #define PMC6_BUS_TRAN_BURST 0x6e
! 479: #define PMC6_BUS_TRAN_ANY 0x70
! 480: #define PMC6_BUS_TRAN_MEM 0x6f
! 481: #define PMC6_BUS_DATA_RCV 0x64
! 482: #define PMC6_BUS_BNR_DRV 0x61
! 483: #define PMC6_BUS_HIT_DRV 0x7a
! 484: #define PMC6_BUS_HITM_DRDV 0x7b
! 485: #define PMC6_BUS_SNOOP_STALL 0x7e
! 486:
! 487: /* Floating Point Unit */
! 488: #define PMC6_FLOPS 0xc1
! 489: #define PMC6_FP_COMP_OPS_EXE 0x10
! 490: #define PMC6_FP_ASSIST 0x11
! 491: #define PMC6_MUL 0x12
! 492: #define PMC6_DIV 0x12
! 493: #define PMC6_CYCLES_DIV_BUSY 0x14
! 494:
! 495: /* Memory Ordering */
! 496: #define PMC6_LD_BLOCKS 0x03
! 497: #define PMC6_SB_DRAINS 0x04
! 498: #define PMC6_MISALIGN_MEM_REF 0x05
! 499: #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
! 500: #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
! 501:
! 502: /* Instruction Decoding and Retirement */
! 503: #define PMC6_INST_RETIRED 0xc0
! 504: #define PMC6_UOPS_RETIRED 0xc2
! 505: #define PMC6_INST_DECODED 0xd0
! 506: #define PMC6_EMON_KNI_INST_RETIRED 0xd8
! 507: #define PMC6_EMON_KNI_COMP_INST_RET 0xd9
! 508:
! 509: /* Interrupts */
! 510: #define PMC6_HW_INT_RX 0xc8
! 511: #define PMC6_CYCLES_INT_MASKED 0xc6
! 512: #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
! 513:
! 514: /* Branches */
! 515: #define PMC6_BR_INST_RETIRED 0xc4
! 516: #define PMC6_BR_MISS_PRED_RETIRED 0xc5
! 517: #define PMC6_BR_TAKEN_RETIRED 0xc9
! 518: #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
! 519: #define PMC6_BR_INST_DECODED 0xe0
! 520: #define PMC6_BTB_MISSES 0xe2
! 521: #define PMC6_BR_BOGUS 0xe4
! 522: #define PMC6_BACLEARS 0xe6
! 523:
! 524: /* Stalls */
! 525: #define PMC6_RESOURCE_STALLS 0xa2
! 526: #define PMC6_PARTIAL_RAT_STALLS 0xd2
! 527:
! 528: /* Segment Register Loads */
! 529: #define PMC6_SEGMENT_REG_LOADS 0x06
! 530:
! 531: /* Clocks */
! 532: #define PMC6_CPU_CLK_UNHALTED 0x79
! 533:
! 534: /* MMX Unit */
! 535: #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
! 536: #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
! 537: #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
! 538: #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
! 539: #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
! 540: #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
! 541: #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
! 542:
! 543: /* Segment Register Renaming */
! 544: #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
! 545: #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
! 546: #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
! 547:
! 548: /*
! 549: * AMD K7 Event Selector MSR format.
! 550: */
! 551:
! 552: #define K7_EVTSEL_EVENT 0x000000ff
! 553: #define K7_EVTSEL_UNIT 0x0000ff00
! 554: #define K7_EVTSEL_UNIT_SHIFT 8
! 555: #define K7_EVTSEL_USR (1 << 16)
! 556: #define K7_EVTSEL_OS (1 << 17)
! 557: #define K7_EVTSEL_E (1 << 18)
! 558: #define K7_EVTSEL_PC (1 << 19)
! 559: #define K7_EVTSEL_INT (1 << 20)
! 560: #define K7_EVTSEL_EN (1 << 22)
! 561: #define K7_EVTSEL_INV (1 << 23)
! 562: #define K7_EVTSEL_COUNTER_MASK 0xff000000
! 563: #define K7_EVTSEL_COUNTER_MASK_SHIFT 24
! 564:
! 565: /* Segment Register Loads */
! 566: #define K7_SEGMENT_REG_LOADS 0x20
! 567:
! 568: #define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
! 569:
! 570: /* Data Cache Unit */
! 571: #define K7_DATA_CACHE_ACCESS 0x40
! 572: #define K7_DATA_CACHE_MISS 0x41
! 573: #define K7_DATA_CACHE_REFILL 0x42
! 574: #define K7_DATA_CACHE_REFILL_SYSTEM 0x43
! 575: #define K7_DATA_CACHE_WBACK 0x44
! 576: #define K7_L2_DTLB_HIT 0x45
! 577: #define K7_L2_DTLB_MISS 0x46
! 578: #define K7_MISALIGNED_DATA_REF 0x47
! 579: #define K7_SYSTEM_REQUEST 0x64
! 580: #define K7_SYSTEM_REQUEST_TYPE 0x65
! 581:
! 582: #define K7_SNOOP_HIT 0x73
! 583: #define K7_SINGLE_BIT_ECC_ERROR 0x74
! 584: #define K7_CACHE_LINE_INVAL 0x75
! 585: #define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
! 586: #define K7_L2_REQUEST 0x79
! 587: #define K7_L2_REQUEST_BUSY 0x7a
! 588:
! 589: /* Instruction Fetch Unit */
! 590: #define K7_IFU_IFETCH 0x80
! 591: #define K7_IFU_IFETCH_MISS 0x81
! 592: #define K7_IFU_REFILL_FROM_L2 0x82
! 593: #define K7_IFU_REFILL_FROM_SYSTEM 0x83
! 594: #define K7_ITLB_L1_MISS 0x84
! 595: #define K7_ITLB_L2_MISS 0x85
! 596: #define K7_SNOOP_RESYNC 0x86
! 597: #define K7_IFU_STALL 0x87
! 598:
! 599: #define K7_RETURN_STACK_HITS 0x88
! 600: #define K7_RETURN_STACK_OVERFLOW 0x89
! 601:
! 602: /* Retired */
! 603: #define K7_RETIRED_INST 0xc0
! 604: #define K7_RETIRED_OPS 0xc1
! 605: #define K7_RETIRED_BRANCHES 0xc2
! 606: #define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
! 607: #define K7_RETIRED_TAKEN_BRANCH 0xc4
! 608: #define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
! 609: #define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
! 610: #define K7_RETIRED_RESYNC_BRANCH 0xc7
! 611: #define K7_RETIRED_NEAR_RETURNS 0xc8
! 612: #define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
! 613: #define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
! 614:
! 615: /* Interrupts */
! 616: #define K7_CYCLES_INT_MASKED 0xcd
! 617: #define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
! 618: #define K7_HW_INTR_RECV 0xcf
! 619:
! 620: #define K7_INSTRUCTION_DECODER_EMPTY 0xd0
! 621: #define K7_DISPATCH_STALLS 0xd1
! 622: #define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
! 623: #define K7_SERIALIZE 0xd3
! 624: #define K7_SEGMENT_LOAD_STALL 0xd4
! 625: #define K7_ICU_FULL 0xd5
! 626: #define K7_RESERVATION_STATIONS_FULL 0xd6
! 627: #define K7_FPU_FULL 0xd7
! 628: #define K7_LS_FULL 0xd8
! 629: #define K7_ALL_QUIET_STALL 0xd9
! 630: #define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
! 631:
! 632: #define K7_BP0_MATCH 0xdc
! 633: #define K7_BP1_MATCH 0xdd
! 634: #define K7_BP2_MATCH 0xde
! 635: #define K7_BP3_MATCH 0xdf
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