Annotation of sys/arch/armish/stand/boot/machdep.c, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: machdep.c,v 1.3 2006/07/30 20:46:30 drahn Exp $ */
2:
3: /*
4: * Copyright (c) 2006 Mark Kettenis
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: #include <sys/types.h>
20: #include <arm/pte.h>
21: #include <dev/pci/pcireg.h>
22:
23: #include "libsa.h"
24:
25: #define L1_IDX(va) (((uint32_t)(va)) >> L1_S_SHIFT)
26:
27: #define ATU_OIOWTVR 0xffffe15c
28: #define ATU_ATUCR 0xffffe180
29: #define ATU_PCSR 0xffffe184
30: #define ATU_OCCAR 0xffffe1a4
31: #define ATU_OCCDR 0xffffe1ac
32:
33: #define ATUCR_OUT_EN (1U << 1)
34:
35: #define PCSR_RIB (1U << 5)
36: #define PCSR_RPB (1U << 4)
37:
38: void
39: machdep(void)
40: {
41: uint32_t *pde;
42: uint32_t va;
43:
44: /*
45: * Clean up the mess that RedBoot left us in, amd make sure we
46: * can access the PCI bus.
47: */
48:
49: *((volatile uint32_t *)(ATU_ATUCR)) = ATUCR_OUT_EN;
50:
51: __asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (pde));
52: pde = (uint32_t *)((uint32_t)pde & 0x0fffffff);
53:
54: va = *((volatile uint32_t *)(ATU_OIOWTVR));
55: pde[L1_IDX(va)] = (va & L1_ADDR_BITS) | L1_S_AP(AP_KRWUR) | L1_TYPE_S;
56:
57: /* Start timer */
58: __asm volatile ("mcr p6, 0, %0, c3, c1, 0" :: "r" (0xffffffff));
59: __asm volatile ("mcr p6, 0, %0, c1, c1, 0" :: "r" (0x00000032));
60:
61: cninit();
62:
63: {
64: /*
65: * this code does a device probe on pci space,
66: * It looks for a wd compatible controller.
67: * however when it reads the device register, it does
68: * not check if a bus fault occurs on the access.
69: * Since the bootloader doesn't handle faults, this
70: * crashes the bootloader if it reads a non-existant
71: * device.
72: * The tag computation comes from arm/xscale/i80321_pci.c
73: * i80321_pci_conf_setup()
74: */
75: int device, bar;
76: for (device = 1; device < 4; device++) {
77: u_int32_t tag, result, size;
78: volatile u_int32_t *occar = (u_int32_t *)ATU_OCCAR;
79: volatile u_int32_t *occdr = (u_int32_t *)ATU_OCCDR;
80:
81: tag = 1 << (device + 16) | (device << 11);
82: *occar = tag;
83: result = *occdr;
84: if (result == ~0)
85: continue;
86: *occar = tag | PCI_CLASS_REG;
87: result = *occdr;
88:
89: if (PCI_CLASS(result) != PCI_CLASS_MASS_STORAGE)
90: continue;
91: if (PCI_SUBCLASS(result) != PCI_SUBCLASS_MASS_STORAGE_ATA &&
92: PCI_SUBCLASS(result) != PCI_SUBCLASS_MASS_STORAGE_SATA &&
93: PCI_SUBCLASS(result) != PCI_SUBCLASS_MASS_STORAGE_MISC)
94: continue;
95:
96: *occar = tag | PCI_MAPREG_START;
97: result = *occdr;
98:
99: /* verify result is an IO BAR */
100: if (PCI_MAPREG_TYPE(result) == PCI_MAPREG_TYPE_IO) {
101: extern u_int32_t wdc_base_addr;
102: wdc_base_addr = PCI_MAPREG_MEM_ADDR(result);
103: DPRINTF(("setting wdc_base addr to %x\n",
104: wdc_base_addr));
105: }
106: }
107: }
108:
109: }
110:
111: int
112: main(void)
113: {
114: boot(0);
115: return 0;
116: }
117:
118: void
119: _rtt(void)
120: {
121: *((volatile uint32_t *)(ATU_PCSR)) = PCSR_RIB | PCSR_RPB;
122:
123: printf("RESET FAILED\n");
124: for (;;) ;
125: }
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