Annotation of sys/arch/hp300/dev/dmavar.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: dmavar.h,v 1.7 2005/11/17 23:56:02 miod Exp $ */
2: /* $NetBSD: dmavar.h,v 1.9 1997/04/01 03:10:59 scottr Exp $ */
3:
4: /*
5: * Copyright (c) 1997 Jason R. Thorpe. All rights reserved.
6: * Copyright (c) 1982, 1990, 1993
7: * The Regents of the University of California. All rights reserved.
8: *
9: * Redistribution and use in source and binary forms, with or without
10: * modification, are permitted provided that the following conditions
11: * are met:
12: * 1. Redistributions of source code must retain the above copyright
13: * notice, this list of conditions and the following disclaimer.
14: * 2. Redistributions in binary form must reproduce the above copyright
15: * notice, this list of conditions and the following disclaimer in the
16: * documentation and/or other materials provided with the distribution.
17: * 3. Neither the name of the University nor the names of its contributors
18: * may be used to endorse or promote products derived from this software
19: * without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: * @(#)dmavar.h 8.1 (Berkeley) 6/10/93
34: */
35:
36: #include <sys/queue.h>
37:
38: /* dmago flags */
39: #define DMAGO_BYTE 0x00 /* do byte (8 bit) transfers */
40: #define DMAGO_WORD 0x01 /* do word (16 bit) transfers */
41: #define DMAGO_LWORD 0x02 /* do longword (32 bit) transfers */
42: #define DMAGO_PRI 0x04 /* do "priority" DMA */
43: #define DMAGO_READ 0x08 /* transfer is a read */
44: #define DMAGO_NOINT 0x80 /* don't interrupt on completion */
45:
46: /* dma "controllers" (channels) */
47: #define DMA0 0x1
48: #define DMA1 0x2
49:
50: /*
51: * A DMA queue entry. Initiator drivers each have one of these,
52: * used to queue access to the DMA controller.
53: */
54: struct dmaqueue {
55: TAILQ_ENTRY(dmaqueue) dq_list; /* entry on the queue */
56: int dq_chan; /* OR of channels initiator can use */
57: void *dq_softc; /* initiator's softc */
58:
59: /*
60: * These functions are called to start the initiator when
61: * it has been given the DMA controller, and to stop the
62: * initiator when the DMA controller has stopped.
63: */
64: void (*dq_start)(void *);
65: void (*dq_done)(void *);
66: };
67:
68: #ifdef _KERNEL
69: void dmainit(void);
70: void dmago(int, char *, u_int, int);
71: void dmastop(int);
72: void dmafree(struct dmaqueue *);
73: int dmareq(struct dmaqueue *);
74: void dmacomputeipl(void);
75: #endif /* _KERNEL */
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