Annotation of sys/arch/hp300/dev/if_lereg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: if_lereg.h,v 1.4 2003/06/02 23:27:45 millert Exp $ */
! 2: /* $NetBSD: if_lereg.h,v 1.8 1995/12/10 00:49:36 mycroft Exp $ */
! 3:
! 4: /*
! 5: * Copyright (c) 1982, 1990 The Regents of the University of California.
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. Redistributions in binary form must reproduce the above copyright
! 14: * notice, this list of conditions and the following disclaimer in the
! 15: * documentation and/or other materials provided with the distribution.
! 16: * 3. Neither the name of the University nor the names of its contributors
! 17: * may be used to endorse or promote products derived from this software
! 18: * without specific prior written permission.
! 19: *
! 20: * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
! 21: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
! 22: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
! 23: * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
! 24: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
! 25: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
! 26: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 27: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
! 28: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
! 29: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
! 30: * SUCH DAMAGE.
! 31: *
! 32: * @(#)if_lereg.h 7.1 (Berkeley) 5/8/90
! 33: */
! 34:
! 35: #define LEID 21
! 36:
! 37: /*
! 38: * DIO registers.
! 39: */
! 40: struct lereg0 {
! 41: u_int8_t ler0_pad0;
! 42: volatile u_int8_t ler0_id; /* ID */
! 43: u_int8_t ler0_pad1;
! 44: volatile u_int8_t ler0_status; /* interrupt enable/status */
! 45: };
! 46:
! 47: /*
! 48: * Control and status bits -- lereg0
! 49: */
! 50: #define LE_IE 0x80 /* interrupt enable */
! 51: #define LE_IR 0x40 /* interrupt requested */
! 52: #define LE_LOCK 0x08 /* lock status register */
! 53: #define LE_ACK 0x04 /* ack of lock */
! 54: #define LE_JAB 0x02 /* loss of tx clock (???) */
! 55: #define LE_IPL(x) ((((x) >> 4) & 0x3) + 3)
! 56:
! 57: /*
! 58: * LANCE registers.
! 59: */
! 60: struct lereg1 {
! 61: volatile u_int16_t ler1_rdp; /* data port */
! 62: volatile u_int16_t ler1_rap; /* register select port */
! 63: };
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