Annotation of sys/arch/hppa/include/iomod.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: iomod.h,v 1.17 2005/04/07 00:21:51 mickey Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2000-2004 Michael Shalayeff
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
! 20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 22: * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
! 25: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
! 26: * THE POSSIBILITY OF SUCH DAMAGE.
! 27: */
! 28: /*
! 29: * Copyright (c) 1990 mt Xinu, Inc. All rights reserved.
! 30: * Copyright (c) 1990,1991,1992,1994 University of Utah. All rights reserved.
! 31: *
! 32: * Permission to use, copy, modify and distribute this software is hereby
! 33: * granted provided that (1) source code retains these copyright, permission,
! 34: * and disclaimer notices, and (2) redistributions including binaries
! 35: * reproduce the notices in supporting documentation, and (3) all advertising
! 36: * materials mentioning features or use of this software display the following
! 37: * acknowledgement: ``This product includes software developed by the
! 38: * Computer Systems Laboratory at the University of Utah.''
! 39: *
! 40: * Copyright (c) 1990 mt Xinu, Inc.
! 41: * This file may be freely distributed in any form as long as
! 42: * this copyright notice is included.
! 43: * MTXINU, THE UNIVERSITY OF UTAH, AND CSL PROVIDE THIS SOFTWARE ``AS
! 44: * IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
! 45: * WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND
! 46: * FITNESS FOR A PARTICULAR PURPOSE.
! 47: *
! 48: * CSL requests users of this software to return to csl-dist@cs.utah.edu any
! 49: * improvements that they make and grant CSL redistribution rights.
! 50: *
! 51: * Utah $Hdr: iomod.h 1.6 94/12/14$
! 52: * Author: Jeff Forys (CSS), Dave Slattengren (mtXinu)
! 53: */
! 54:
! 55: #ifndef _MACHINE_IOMOD_H_
! 56: #define _MACHINE_IOMOD_H_
! 57:
! 58: #include <machine/pdc.h>
! 59:
! 60: /*
! 61: * Structures and definitions for I/O Modules on HP-PA (9000/800).
! 62: *
! 63: * Memory layout:
! 64: *
! 65: * 0x00000000 +---------------------------------+
! 66: * | Page Zero |
! 67: * 0x00000800 + - - - - - - - - - - - - - - - - +
! 68: * | |
! 69: * | |
! 70: * | Memory Address Space |
! 71: * | |
! 72: * | |
! 73: * 0xEF000000 +---------------------------------+
! 74: * | |
! 75: * | PDC Address Space |
! 76: * | |
! 77: * 0xF1000000 +---------------------------------+
! 78: * | |
! 79: * | |
! 80: * | I/O Address Space |
! 81: * | |
! 82: * | |
! 83: * 0xFFF80000 + - - - - - - - - - - - - - - - - +
! 84: * | Fixed Physical Address Space |
! 85: * 0xFFFC0000 + - - - - - - - - - - - - - - - - +
! 86: * | Local Broadcast Address Space |
! 87: * 0xFFFE0000 + - - - - - - - - - - - - - - - - +
! 88: * | Global Broadcast Address Space |
! 89: * 0xFFFFFFFF +---------------------------------+
! 90: *
! 91: * "Memory Address Space" is used by memory modules,
! 92: * "Page Zero" is described below.
! 93: * "PDC Address Space" is used by Processor-Dependent Code.
! 94: * "I/O Address Space" is used by I/O modules (and is not cached),
! 95: * "Fixed Physical" is used by modules on the central bus,
! 96: * "Local Broadcast" is used to reach all modules on the same bus, and
! 97: * "Global Broadcast" is used to reach all modules (thru bus converters).
! 98: *
! 99: * SPA space (see below) ranges from 0xF1000000 thru 0xFFFC0000.
! 100: */
! 101:
! 102: #define PDC_LOW 0xEF000000 /* define some ranges */
! 103: #define PDC_HIGH 0xF1000000
! 104: #define FPA_LOW 0xFFF80000
! 105: #define FPA_HIGH 0xFFFC0000
! 106: #define SPA_LOW 0xF1000000
! 107: #define SPA_HIGH 0xFFFC0000
! 108: #define SGC_LOW 0xF4000000
! 109: #define SGC_HIGH 0xFA000000
! 110:
! 111: #define FPA_IOMOD ((FPA_HIGH-FPA_LOW)/sizeof(struct iomod))
! 112: #define MAXMODBUS ((int)(FPA_IOMOD)) /* maximum modules/bus */
! 113:
! 114: /* size of HPA space for any device */
! 115: #define IOMOD_HPASIZE 0x1000
! 116:
! 117: /* ASP prom offset for an lan stattion id */
! 118: #define ASP_PROM (0xf0810000)
! 119:
! 120: /* offset to the device-specific registers,
! 121: * basically sizeof(struct iomod) (see later)
! 122: */
! 123: #define IOMOD_DEVOFFSET 0x800
! 124:
! 125: #if !defined(_LOCORE)
! 126:
! 127: /*
! 128: * The first 2K of Soft Physical Address space on the Initial Memory Module
! 129: * is aptly called "page zero". The following structure defines the format
! 130: * of page zero. Individual members of this structure should be accessed
! 131: * as "PAGE0->member".
! 132: */
! 133:
! 134: #define PAGE0 ((struct pagezero *)0) /* can't get any lower than this! */
! 135:
! 136: struct pagezero {
! 137: /* [0x000] Initialize Vectors */
! 138: int ivec_special; /* must be zero */
! 139: u_int ivec_mempf; /* powerfail recovery software */
! 140: u_int ivec_toc; /* exec'd after Transfer Of Control */
! 141: u_int ivec_toclen; /* bytes of ivec_toc code */
! 142: u_int ivec_rendz; /* exec'd after Rendezvous Signal */
! 143: u_int ivec_mempflen; /* bytes of ivec_mempf code */
! 144: u_int ivec_resv[2]; /* (reserved) */
! 145: u_int ivec_mbz; /* must be zero */
! 146: u_int ivec_resv2[7]; /* (reserved) */
! 147:
! 148: /* [0x040] Processor Dependent */
! 149: union {
! 150: u_int pd_Resv1[112]; /* (reserved) processor dependent */
! 151: struct { /* Viper-specific data */
! 152: u_int v_Resv1[39];
! 153: u_int v_Ctrlcpy; /* copy of Viper `vi_control' */
! 154: u_int v_Resv2[72];
! 155: } pd_Viper;
! 156: } pz_Pdep;
! 157:
! 158: /* [0x200] IODC Data Area Descriptors
! 159: use PDC_ALLOC to allocate these memory regions */
! 160: u_int iodc_cons_base; /* */
! 161: u_int iodc_cons_size; /* */
! 162: u_int iodc_kbrd_base; /* */
! 163: u_int iodc_kbrd_size; /* */
! 164: u_int iodc_boot_base; /* */
! 165: u_int iodc_boot_size; /* */
! 166:
! 167: /* [0x218] */
! 168: u_int resv1[0x41];
! 169:
! 170: /* [0x31C] Capability Flags */
! 171: u_int cap_flags; /* system capabitlities */
! 172: #define HPPA_CAP_WIDESCSI 0x00000001
! 173:
! 174: /* [0x320] Keyboard Extensions */
! 175: u_int kbrd_ext[2];
! 176:
! 177: /* [0x328] Boot Device Extensions */
! 178: u_int boot_ext[2];
! 179:
! 180: /* [0x330] Console/Display Extensions */
! 181: u_int cons_ext[2];
! 182:
! 183: /* [0x338] Initial Memory Module Extensions */
! 184: u_int imm_ext[2];
! 185:
! 186: /* [0x340] Memory Configuration */
! 187: u_int memc_cont_l; /* memc_cont low part */
! 188: u_int memc_phsize_l; /* memc_phsize low part */
! 189: u_int memc_adsize_l; /* memc_adsize low part */
! 190: u_int memc_resv; /* (reserved) */
! 191: u_int memc_cont; /* bytes of contiguous valid memory */
! 192: u_int memc_phsize; /* bytes of valid physical memory */
! 193: u_int memc_adsize; /* bytes of SPA space used by PDC */
! 194: u_int memc_hpa_h; /* HPA of CPU (high) */
! 195:
! 196: /* [0x360] Miscellaneous */
! 197: struct boot_err mem_be[8]; /* boot errors (see above) */
! 198: u_int mem_free; /* first free phys. memory location */
! 199: u_int mem_hpa; /* HPA of CPU */
! 200: u_int mem_pdc; /* PDC entry point */
! 201: u_int mem_10msec; /* # of Interval Timer ticks in 10msec*/
! 202:
! 203: /* [0x390] Initial Memory Module */
! 204: u_int imm_hpa; /* HPA of Initial Memory module */
! 205: u_int imm_soft_boot; /* 0 == hard boot, 1 == soft boot */
! 206: u_int imm_spa_size; /* bytes of SPA in IMM */
! 207: u_int imm_max_mem; /* bytes of mem in IMM (<= spa_size) */
! 208:
! 209: /* [0x3A0] Boot Console/Display, Device, and Keyboard */
! 210: struct pz_device mem_cons; /* description of console device */
! 211: struct pz_device mem_boot; /* description of boot device */
! 212: struct pz_device mem_kbd; /* description of keyboard device */
! 213:
! 214: /* [0x430] Reserved */
! 215: u_int resv2[116]; /* (reserved) */
! 216:
! 217: /* [0x600] Processor Dependent */
! 218: u_int pd_resv2[128]; /* (reserved) processor dependent */
! 219: };
! 220: #define v_ctrlcpy pz_Pdep.pd_Viper.v_Ctrlcpy
! 221:
! 222:
! 223: /*
! 224: * Every module has 4K-bytes of address space associated with it.
! 225: * A Hard Physical Address (HPA) can be broken down as follows.
! 226: *
! 227: * Since this is an I/O space, the high 4 bits are always 1's.
! 228: *
! 229: * The "flex" address specifies which bus a module is on; there are
! 230: * 256K-bytes of HPA space for each bus, however only values from
! 231: * 64 - 1022 are valid for the "flex" field (1022 designates the
! 232: * central bus). The "flex" addr is set at bus configuration time.
! 233: *
! 234: * The "fixed" address specifies a particular module on the same
! 235: * bus (i.e. among modules with the same "flex" address). This
! 236: * value can also be found in "device_path.dp_mod" in "pdc.h".
! 237: *
! 238: * A modules HPA space consists of 2 pages; the "up" bit specifies
! 239: * which of these pages is being addressed. In general, the lower
! 240: * page is privileged and the upper page it module-type dependent.
! 241: *
! 242: */
! 243:
! 244: struct hpa {
! 245: u_int hpa_ones: 4, /* must be 1's; this is an I/O space addr */
! 246: hpa_flex:10, /* bus address for this module */
! 247: hpa_fixed:6, /* location of module on bus */
! 248: hpa_up : 1, /* 1 == upper page, 0 == lower page */
! 249: hpa_set : 5, /* register set */
! 250: hpa_reg : 4, /* register number within a register set */
! 251: hpa_zeros:2; /* must be 0's; addrs are word aligned */
! 252: };
! 253:
! 254:
! 255: /*
! 256: * Certain modules require additional memory (i.e. more than that
! 257: * provided by the HPA space). A Soft Physical Address (SPA) can be
! 258: * broken down as follows, on a module-type specific basis (either
! 259: * Memory SPA or I/O SPA).
! 260: *
! 261: * SPA space must be a power of 2, and aligned accordingly. The IODC
! 262: * provides all information needed by software to configure SPA space
! 263: * for a particular module.
! 264: */
! 265:
! 266: struct memspa {
! 267: u_int spa_page:21, /* page of memory */
! 268: spa_off :11; /* offset into memory page */
! 269: };
! 270:
! 271: struct iospa {
! 272: u_int spa_ones: 4, /* must be 1's; this is an I/O space addr */
! 273: spa_iopg:17, /* page in I/O address space */
! 274: spa_set : 5, /* register set */
! 275: spa_reg : 4, /* register number within a register set */
! 276: spa_mode: 2; /* aligned according to bus transaction mode */
! 277: };
! 278:
! 279:
! 280: /*
! 281: * It is possible to send a command to all modules on a particular bus
! 282: * (local broadcast), or all modules (global broadcast). A Broadcast
! 283: * Physical Address (BPA) can be broken down as follows.
! 284: *
! 285: * Read and Clear transactions are not allowed in BPA space. All pages
! 286: * in BPA space are privileged.
! 287: */
! 288:
! 289: struct bpa {
! 290: u_int bpa_ones:14, /* must be 1's; this is in BPA space */
! 291: bpa_gbl : 1, /* 0 == local, 1 == global broadcast */
! 292: bpa_page: 6, /* page in local/global BPA space */
! 293: bpa_set : 5, /* register set */
! 294: bpa_reg : 4, /* register number within a register set */
! 295: bpa_zeros:2; /* must be 0's; addrs are word aligned */
! 296: };
! 297:
! 298:
! 299: /*
! 300: * All I/O and Memory modules have 4K-bytes of HPA space associated with
! 301: * it (described above), however not all modules implement every register.
! 302: * The first 2K-bytes of registers are "privileged".
! 303: *
! 304: * (WO) == Write Only, (RO) == Read Only
! 305: */
! 306:
! 307: struct iomod {
! 308: /* SRS (Supervisor Register Set) */
! 309: u_int io_eir; /* (WO) interrupt CPU; set bits in EIR CR */
! 310: u_int io_eim; /* (WO) External Interrupt Message address */
! 311: u_int io_dc_rw; /* write address of IODC to read IODC data */
! 312: u_int io_ii_rw; /* read/clear external intrpt msg (bit-26) */
! 313: u_int io_dma_link; /* pointer to "next quad" in DMA chain */
! 314: u_int io_dma_command; /* (RO) chain command to exec on "next quad" */
! 315: u_int io_dma_address; /* (RO) start of DMA */
! 316: u_int io_dma_count; /* (RO) number of bytes remaining to xfer */
! 317: u_int io_flex; /* (WO) HPA flex addr, LSB: bus master flag */
! 318: u_int io_spa; /* (WO) SPA space; 0-20:addr, 24-31:iodc_spa */
! 319: u_int resv1[2]; /* (reserved) */
! 320: u_int io_command; /* (WO) module commands (see below) */
! 321: u_int io_status; /* (RO) error returns (see below) */
! 322: u_int io_control; /* memory err logging (bit-9), bc forwarding */
! 323: u_int io_test; /* (RO) self-test information */
! 324: /* ARS (Auxiliary Register Set) */
! 325: u_int io_err_sadd; /* (RO) slave bus error or memory error addr */
! 326: u_int chain_addr; /* start address of chain RAM */
! 327: u_int sub_mask_clr; /* ignore intrpts on sub-channel (bitmask) */
! 328: u_int sub_mask_set; /* service intrpts on sub-channel (bitmask) */
! 329: u_int diagnostic; /* diagnostic use (reserved) */
! 330: u_int resv2[2]; /* (reserved) */
! 331: u_int nmi_address; /* address to send data to when NMI detected */
! 332: u_int nmi_data; /* NMI data to be sent */
! 333: u_int resv3[3]; /* (reserved) */
! 334: u_int io_mem_low; /* bottom of memory address range */
! 335: u_int io_mem_high; /* top of memory address range */
! 336: u_int io_io_low; /* bottom of I/O HPA address Range */
! 337: u_int io_io_high; /* top of I/O HPA address Range */
! 338:
! 339: u_int priv_trs[160]; /* TRSes (Type-dependent Reg Sets) */
! 340:
! 341: u_int priv_hvrs[320]; /* HVRSes (HVERSION-dependent Register Sets) */
! 342:
! 343: u_int hvrs[512]; /* HVRSes (HVERSION-dependent Register Sets) */
! 344: };
! 345: #endif /* !_LOCORE */
! 346:
! 347: /* primarily for a "reboot" and "_rtt" routines */
! 348: #define iomod_command (4*12)
! 349:
! 350: /* io_flex */
! 351: #define DMA_ENABLE 0x1 /* flex register enable DMA bit */
! 352:
! 353: /* io_spa */
! 354: #define IOSPA(spa,iodc_data) \
! 355: ((volatile caddr_t) \
! 356: (spa | iodc_data.iodc_spa_shift | iodc_data.iodc_spa_enb << 5 | \
! 357: iodc_data.iodc_spa_pack << 6 | iodc_data.iodc_spa_io << 7))
! 358:
! 359: /* io_command */
! 360: #define CMD_STOP 0 /* halt any I/O, enable diagnostic access */
! 361: #define CMD_FLUSH 1 /* abort DMA */
! 362: #define CMD_CHAIN 2 /* initiate DMA */
! 363: #define CMD_CLEAR 3 /* clear errors */
! 364: #define CMD_RESET 5 /* reset any module */
! 365:
! 366: /* io_status */
! 367: #define IO_ERR_MEM_SL 0x10000 /* SPA space lost or corrupted */
! 368: #define IO_ERR_MEM_SE 0x00200 /* severity: minor */
! 369: #define IO_ERR_MEM_HE 0x00100 /* severity: affects invalid parts */
! 370: #define IO_ERR_MEM_FE 0x00080 /* severity: bad */
! 371: #define IO_ERR_MEM_RY 0x00040 /* IO_COMMAND register ready for command */
! 372: #define IO_ERR_DMA_DG 0x00010 /* module in diagnostic mode */
! 373: #define IO_ERR_DMA_PW 0x00004 /* Power Failing */
! 374: #define IO_ERR_DMA_PL 0x00002 /* Power Lost */
! 375: #define IO_ERR_VAL(x) (((x) >> 10) & 0x3f)
! 376: #define IO_ERR_DEPEND 0 /* unspecified error */
! 377: #define IO_ERR_SPA 1 /* (module-type specific) */
! 378: #define IO_ERR_INTERNAL 2 /* (module-type specific) */
! 379: #define IO_ERR_MODE 3 /* invlaid mode or address space mapping */
! 380: #define IO_ERR_ERROR_M 4 /* bus error (master detect) */
! 381: #define IO_ERR_DPARITY_S 5 /* data parity (slave detect) */
! 382: #define IO_ERR_PROTO_M 6 /* protocol error (master detect) */
! 383: #define IO_ERR_ADDRESS 7 /* no slave acknowledgement in transaction */
! 384: #define IO_ERR_MORE 8 /* device transferred more data than expected */
! 385: #define IO_ERR_LESS 9 /* device transferred less data than expected */
! 386: #define IO_ERR_SAPARITY 10 /* slave addrss phase parity */
! 387: #define IO_ERR_MAPARITY 11 /* master address phase parity */
! 388: #define IO_ERR_MDPARITY 12 /* mode phase parity */
! 389: #define IO_ERR_STPARITY 13 /* status phase parity */
! 390: #define IO_ERR_CMD 14 /* unimplemented I/O Command */
! 391: #define IO_ERR_BUS 15 /* generic bus error */
! 392: #define IO_ERR_CORR 24 /* correctable memory error */
! 393: #define IO_ERR_UNCORR 25 /* uncorrectable memory error */
! 394: #define IO_ERR_MAP 26 /* equivalent to IO_ERR_CORR */
! 395: #define IO_ERR_LINK 28 /* Bus Converter "link" (connection) error */
! 396: #define IO_ERR_CCMD 32 /* Illegal DMA command */
! 397: #define IO_ERR_ERROR_S 52 /* bus error (slave detect) */
! 398: #define IO_ERR_DPARITY_M 53 /* data parity (master detect) */
! 399: #define IO_ERR_PROTOCOL 54 /* protocol error (slave detect) */
! 400: #define IO_ERR_SELFTEST 58 /* (module-type specific) */
! 401: #define IO_ERR_BUSY 59 /* slave was busy too often or too long */
! 402: #define IO_ERR_RETRY 60 /* "busied" transaction not retried soon enuf */
! 403: #define IO_ERR_ACCESS 61 /* illegal register access */
! 404: #define IO_ERR_IMPROP 62 /* "improper" data written */
! 405: #define IO_ERR_UNKNOWN 63
! 406:
! 407: /* io_control (memory) */
! 408: #define IO_CTL_MEMINIT 0x0 /* prevent some bus errors during memory init */
! 409: #define IO_CTL_MEMOKAY 0x100 /* enable all bus error logging */
! 410:
! 411: /* io_spa */
! 412: #define SPA_ENABLE 0x20 /* io_spa register enable spa bit */
! 413:
! 414: #endif /* _MACHINE_IOMOD_H_ */
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