Annotation of sys/arch/mac68k/include/psc.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: psc.h,v 1.5 2004/12/14 14:50:55 martin Exp $ */
! 2: /* $NetBSD: psc.h,v 1.5 2004/03/26 12:15:46 wiz Exp $ */
! 3:
! 4: /*-
! 5: * Copyright (c) 1997 David Huang <khym@azeotrope.org>
! 6: * All rights reserved.
! 7: *
! 8: * Redistribution and use in source and binary forms, with or without
! 9: * modification, are permitted provided that the following conditions
! 10: * are met:
! 11: * 1. Redistributions of source code must retain the above copyright
! 12: * notice, this list of conditions and the following disclaimer.
! 13: * 2. The name of the author may not be used to endorse or promote products
! 14: * derived from this software without specific prior written permission
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
! 18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
! 19: * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
! 20: * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
! 21: * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
! 22: * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
! 23: * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
! 24: * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
! 25: * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! 26: *
! 27: */
! 28:
! 29: /*
! 30: * Some register definitions for the PSC, present only on the
! 31: * Centris/Quadra 660av and the Quadra 840av.
! 32: */
! 33:
! 34: extern volatile u_int8_t *PSCBase;
! 35:
! 36: #define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
! 37: #define psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
! 38: #define psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
! 39:
! 40: void psc_init(void);
! 41:
! 42: int add_psc_lev3_intr(void (*)(void *), void *);
! 43: int add_psc_lev4_intr(int, int (*)(void *), void *);
! 44: int add_psc_lev5_intr(int, void (*)(void *), void *);
! 45: int add_psc_lev6_intr(int, void (*)(void *), void *);
! 46:
! 47: int remove_psc_lev3_intr(void);
! 48: int remove_psc_lev4_intr(int);
! 49: int remove_psc_lev5_intr(int);
! 50: int remove_psc_lev6_intr(int);
! 51:
! 52: /*
! 53: * Reading an interrupt status register returns a mask of the
! 54: * currently interrupting devices (one bit per device). Reading an
! 55: * interrupt enable register returns a mask of the currently enabled
! 56: * devices. Writing an interrupt enable register with the MSB set
! 57: * enables the interrupts in the lower 4 bits, while writing with the
! 58: * MSB clear disables the corresponding interrupts.
! 59: * e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
! 60: * and 2, write 0x02 to disable device 1.
! 61: *
! 62: * Level 3 device 0 is MACE
! 63: * Level 4 device 0 is 3210 DSP?
! 64: * Level 4 device 1 is SCC channel A (modem port)
! 65: * Level 4 device 2 is SCC channel B (printer port)
! 66: * Level 4 device 3 is MACE DMA completion
! 67: * Level 5 device 0 is 3210 DSP?
! 68: * Level 5 device 1 is 3210 DSP?
! 69: * Level 6 device 0 is ?
! 70: * Level 6 device 1 is ?
! 71: * Level 6 device 2 is ?
! 72: */
! 73:
! 74: /* PSC interrupt registers */
! 75: #define PSC_ISR_BASE 0x100 /* ISR is BASE + 0x10 * level */
! 76: #define PSC_IER_BASE 0x104 /* IER is BASE + 0x10 * level */
! 77:
! 78: #define PSC_LEV3_ISR 0x130 /* level 3 interrupt status register */
! 79: #define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */
! 80: #define PSCINTR_ENET 0 /* Ethernet interrupt */
! 81:
! 82: #define PSC_LEV4_ISR 0x140 /* level 4 interrupt status register */
! 83: #define PSC_LEV4_IER 0x144 /* level 4 interrupt enable register */
! 84: #define PSCINTR_SCCA 1 /* SCC channel A interrupt */
! 85: #define PSCINTR_SCCB 2 /* SCC channel B interrupt */
! 86: #define PSCINTR_ENET_DMA 3 /* Ethernet DMA completion interrupt */
! 87:
! 88: #define PSC_LEV5_ISR 0x150 /* level 5 interrupt status register */
! 89: #define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */
! 90:
! 91: #define PSC_LEV6_ISR 0x160 /* level 6 interrupt status register */
! 92: #define PSC_LEV6_IER 0x164 /* level 6 interrupt enable register */
! 93:
! 94: /* PSC DMA channel control registers */
! 95: #define PSC_CTLBASE 0xc00
! 96:
! 97: #define PSC_SCSI_CTL 0xc00 /* SCSI control/status */
! 98: #define PSC_ENETRD_CTL 0xc10 /* MACE receive DMA channel control/status */
! 99: #define PSC_ENETWR_CTL 0xc20 /* MACE transmit DMA channel control/status */
! 100: #define PSC_FDC_CTL 0xc30 /* Floppy disk */
! 101: #define PSC_SCCA_CTL 0xc40 /* SCC channel A */
! 102: #define PSC_SCCB_CTL 0xc50 /* SCC channel B */
! 103: #define PSC_SCCATX_CTL 0xc60 /* SCC channel A transmit */
! 104:
! 105: /* PSC DMA channels */
! 106: #define PSC_ADDRBASE 0x1000
! 107: #define PSC_LENBASE 0x1004
! 108: #define PSC_CMDBASE 0x1008
! 109:
! 110: #define PSC_SCSI_ADDR 0x1000 /* SCSI DMA address register */
! 111: #define PSC_SCSI_LEN 0x1004 /* SCSI DMA buffer count */
! 112: #define PSC_SCSI_CMD 0x1008 /* SCSI DMA command register */
! 113: #define PSC_ENETRD_ADDR 0x1020 /* MACE receive DMA address register */
! 114: #define PSC_ENETRD_LEN 0x1024 /* MACE receive DMA buffer count */
! 115: #define PSC_ENETRD_CMD 0x1028 /* MACE receive DMA command register */
! 116: #define PSC_ENETWR_ADDR 0x1040 /* MACE transmit DMA address register */
! 117: #define PSC_ENETWR_LEN 0x1044 /* MACE transmit DMA length */
! 118: #define PSC_ENETWR_CMD 0x1048 /* MACE transmit DMA command register */
! 119:
! 120: /*
! 121: * PSC DMA channels are controlled by two sets of registers (see p.29
! 122: * of the Quadra 840av and Centris 660av Developer Note). Add the
! 123: * following offsets to get the desired register set.
! 124: */
! 125: #define PSC_SET0 0x00
! 126: #define PSC_SET1 0x10
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