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File: [local] / sys / arch / mvmeppc / dev / openpicreg.h (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:07:44 2008 UTC (16 years, 6 months ago) by nbrk
Import of OpenBSD 4.2 release kernel tree with initial code to support Jornada 720/728, StrongARM 1110-based handheld PC. At this point kernel roots on NFS and boots into vfs_mountroot() and traps. What is supported: - glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode (needs some palette tweaks for non black/white/blue colors, i think) - saic, SA11x0 interrupt controller (needs cleanup) - sacom, SA11x0 UART (supported only as boot console for now) - SA11x0 GPIO controller fully supported (but can't handle multiple interrupt handlers on one gpio pin) - sassp, SSP port on SA11x0 that attaches spibus - Jornada microcontroller (jmcu) to control kbd, battery, etc throught the SPI bus (wskbd attaches on jmcu, but not tested) - tod functions seem work - initial code for SA-1111 (chip companion) : this is TODO Next important steps, i think: - gpio and intc on sa1111 - pcmcia support for sa11x0 (and sa1111 help logic) - REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs) - root on wd0! (using already supported PCMCIA-ATA) |
/* $OpenBSD: openpicreg.h,v 1.2 2001/07/04 08:31:31 niklas Exp $ */ /* $NetBSD: openpicreg.h,v 1.1 2000/02/14 12:45:53 tsubai Exp $ */ /*- * Copyright (c) 2000 Tsubai Masanari. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * GLOBAL/TIMER register (IDU base + 0x1000) */ /* feature reporting reg 0 */ #define OPENPIC_FEATURE 0x1000 /* global config reg 0 */ #define OPENPIC_CONFIG 0x1020 #define OPENPIC_CONFIG_RESET 0x80000000 #define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 /* vendor ID */ #define OPENPIC_VENDOR_ID 0x1080 /* processor initialization reg */ #define OPENPIC_PROC_INIT 0x1090 /* IPI vector/priority reg */ #define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) /* spurious intr. vector */ #define OPENPIC_SPURIOUS_VECTOR 0x10e0 /* * INTERRUPT SOURCE register (IDU base + 0x10000) */ /* interrupt vector/priority reg */ #define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) #define OPENPIC_SENSE_LEVEL 0x00400000 #define OPENPIC_SENSE_EDGE 0x00000000 #define OPENPIC_POLARITY_POSITIVE 0x00800000 #define OPENPIC_POLARITY_NEGATIVE 0x00000000 #define OPENPIC_IMASK 0x80000000 #define OPENPIC_ACTIVITY 0x40000000 #define OPENPIC_PRIORITY_MASK 0x000f0000 #define OPENPIC_PRIORITY_SHIFT 16 #define OPENPIC_VECTOR_MASK 0x000000ff /* interrupt destination cpu */ #define OPENPIC_SRC_DEST(irq) (0x10010 + (irq) * 0x20) #define CPU(x) (1 << (x)) /* * PROCESSOR register (IDU base + 0x20000) */ /* IPI command reg */ #define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) /* current task priority reg */ #define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) #define OPENPIC_CPU_PRIORITY_MASK 0x0000000f /* interrupt acknowledge reg */ #define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) /* end of interrupt reg */ #define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000)