Annotation of sys/arch/mvmeppc/dev/ravenreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: ravenreg.h,v 1.4 2004/11/19 22:11:04 miod Exp $ */
2:
3: /*
4: * Copyright (c) 2001 Steve Murphree, Jr.
5: *
6: * Redistribution and use in source and binary forms, with or without
7: * modification, are permitted provided that the following conditions
8: * are met:
9: * 1. Redistributions of source code must retain the above copyright
10: * notice, this list of conditions and the following disclaimer.
11: * 2. Redistributions in binary form must reproduce the above copyright
12: * notice, this list of conditions and the following disclaimer in the
13: * documentation and/or other materials provided with the distribution.
14: * 3. All advertising materials mentioning features or use of this software
15: * must display the following acknowledgement:
16: * This product includes software developed under OpenBSD for RTMX Inc
17: * by Per Fogelstrom, Opsycon AB.
18: * 4. The name of the author may not be used to endorse or promote products
19: * derived from this software without specific prior written permission.
20: *
21: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
22: * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
25: * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31: * SUCH DAMAGE.
32: *
33: *
34: * ravenreg.h: Motorola 'Raven' PowerPC to PCI bridge controller
35: */
36:
37: #ifndef _MACHINE_RAVENREG_H_
38: #define _MACHINE_RAVENREG_H_
39:
40: #define RAVEN_BASE 0xfeff0000
41: #define RAVEN_SIZE 0x00001000
42:
43: #define RAVEN_VENDOR 0x00000000
44: #define RAVEN_MAGIC 0x10574801 /* vendor information */
45: #define RAVEN_DEVICE 0x00000002
46: #define RAVEN_REVID 0x00000005
47: #define RAVEN_GCSR 0x00000008
48: #define RAVEN_FEAT 0x0000000a
49: #define RAVEN_MARB 0x0000000e
50: #define RAVEN_PIACK 0x00000030
51:
52: #define RAVEN_MSADD0 0x00000040
53: #define RAVEN_MSADD0_PREP 0xc000fcff
54: #define RAVEN_MSOFF0 0x00000044
55: #define RAVEN_MSOFF0_PREP 0x400000c2
56: #define RAVEN_MSADD1 0x00000048
57: #define RAVEN_MSADD1_PREP 0x00000000
58: #define RAVEN_MSOFF1 0x0000004c
59: #define RAVEN_MSOFF1_PREP 0x00000002
60: #define RAVEN_MSADD2 0x00000050
61: #define RAVEN_MSADD2_PREP 0x00000000
62: #define RAVEN_MSOFF2 0x00000054
63: #define RAVEN_MSOFF2_PREP 0x00000002
64: #define RAVEN_MSADD3 0x00000058
65: #define RAVEN_MSADD3_PREP 0x8000bfff
66: #define RAVEN_MSOFF3 0x0000005c
67: #define RAVEN_MSOFF3_PREP 0x800000c0
68:
69: /* Where we map the PCI memory space - MAP A*/
70: #define RAVEN_V_PCI_MEM_SPACE 0xc0000000 /* Virtual */
71: #define RAVEN_P_PCI_MEM_SPACE 0xc0000000 /* Physical */
72:
73: /* Where we map the PCI I/O space - MAP A*/
74: #define RAVEN_P_ISA_IO_SPACE 0x80000000
75: #define RAVEN_V_ISA_IO_SPACE 0x80000000
76: #define RAVEN_V_PCI_IO_SPACE 0x80000000
77: #define RAVEN_P_PCI_IO_SPACE 0x80000000
78:
79: #define PREP_CONFIG_ADD 0x80000cf8
80: #define PREP_CONFIG_DAT 0x80000cfc
81:
82: /* Where we map the config space */
83: #define RAVEN_PCI_CONF_SPACE (RAVEN_V_ISA_IO_SPACE + 0x00800000)
84:
85: /* Where we map the PCI memory space - MAP B*/
86: #define RAVEN_P_PCI_MEM_SPACE_MAP_B 0x80000000 /* Physical */
87:
88: /* Where we map the PCI I/O space - MAP B*/
89: #define RAVEN_P_PCI_IO_SPACE_MAP_B 0xfe000000
90:
91: /* offsets from base pointer */
92: #define RAVEN_REGOFFS(x) ((x) | 0x80000000)
93:
94: /* Where PCI devices sees CPU memory. */
95: #define RAVEN_PCI_CPUMEM 0x80000000
96:
97: #define RAVEN_PCI_VENDOR 0x00
98: #define RAVEN_PCI_DEVICE 0x02
99: #define RAVEN_PCI_CMD 0x04
100: #define RAVEN_PCI_STAT 0x06
101: #define RAVEN_PCI_REVID 0x08
102: #define RAVEN_PCI_IO 0x10
103: #define RAVEN_PCI_MEM 0x14
104: #define RAVEN_PCI_MEM_VAL 0x3c000000 /* PREP PCI memory space */
105: #define RAVEN_PCI_PSADD0 0x80
106: #define RAVEN_PCI_PSADD0_VAL 0x8000fbff
107: #define RAVEN_PCI_PSOFF0 0x84
108: #define RAVEN_PCI_PSOFF0_VAL 0x800000f0
109: #define RAVEN_PCI_PSADD1 0x88
110: #define RAVEN_PCI_PSADD1_VAL 0x00000000
111: #define RAVEN_PCI_PSOFF1 0x8C
112: #define RAVEN_PCI_PSOFF1_VAL 0x00000000
113: #define RAVEN_PCI_PSADD2 0x90
114: #define RAVEN_PCI_PSADD2_VAL 0x00000000
115: #define RAVEN_PCI_PSOFF2 0x94
116: #define RAVEN_PCI_PSOFF2_VAL 0x00000000
117: #define RAVEN_PCI_PSADD3 0x98
118: #define RAVEN_PCI_PSADD3_VAL 0x00000000
119: #define RAVEN_PCI_PSOFF3 0x9C
120: #define RAVEN_PCI_PSOFF3_VAL 0x00000000
121:
122: #define RAVEN_CMD_IOSP 0x0001
123: #define RAVEN_CMD_MEMSP 0x0002
124: #define RAVEN_CMD_MASTR 0x0004
125:
126: /* How much ISA space we'll map initially */
127: #define ISA_SIZE PAGE_SIZE
128:
129: #endif /* _MACHINE_RAVENREG_H_ */
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