Annotation of sys/arch/sparc64/dev/sab82532reg.h, Revision 1.1
1.1 ! nbrk 1: /* $OpenBSD: sab82532reg.h,v 1.3 2003/06/02 20:02:49 jason Exp $ */
! 2:
! 3: /*
! 4: * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
! 5: * All rights reserved.
! 6: *
! 7: * Redistribution and use in source and binary forms, with or without
! 8: * modification, are permitted provided that the following conditions
! 9: * are met:
! 10: * 1. Redistributions of source code must retain the above copyright
! 11: * notice, this list of conditions and the following disclaimer.
! 12: * 2. Redistributions in binary form must reproduce the above copyright
! 13: * notice, this list of conditions and the following disclaimer in the
! 14: * documentation and/or other materials provided with the distribution.
! 15: *
! 16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
! 17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
! 18: * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
! 19: * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
! 20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
! 21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
! 22: * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
! 23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
! 24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
! 25: * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
! 26: * POSSIBILITY OF SUCH DAMAGE.
! 27: *
! 28: * Effort sponsored in part by the Defense Advanced Research Projects
! 29: * Agency (DARPA) and Air Force Research Laboratory, Air Force
! 30: * Materiel Command, USAF, under agreement number F30602-01-2-0537.
! 31: *
! 32: */
! 33:
! 34: /*
! 35: * Register definitions for SAB82532 based on "Enhanced Serial Communication
! 36: * Controller ESCC2 Version 3.2 User's Manual 07.96" from:
! 37: * http://www.infineon.com
! 38: */
! 39:
! 40: #define SAB_NCHAN 2 /* number of channels */
! 41: #define SAB_CHANLEN 0x40 /* length of channel register set */
! 42:
! 43: #define SAB_CHAN_A 0x00 /* channel A register offset */
! 44: #define SAB_CHAN_B 0x40 /* channel B register offset */
! 45:
! 46: #define SAB_RFIFO 0x00 /* r: rx fifo */
! 47: #define SAB_XFIFO 0x00 /* w: tx fifo */
! 48: #define SAB_STAR 0x20 /* r: status register */
! 49: #define SAB_CMDR 0x20 /* w: command register */
! 50: #define SAB_MODE 0x22 /* rw: mode register */
! 51: #define SAB_TIMR 0x23 /* rw: timer register */
! 52: #define SAB_XON 0x24 /* rw: xon character */
! 53: #define SAB_XOFF 0x25 /* rw: xoff character */
! 54: #define SAB_TCR 0x26 /* rw: termination character */
! 55: #define SAB_DAFO 0x27 /* rw: data format */
! 56: #define SAB_RFC 0x28 /* rw: rfifo control register */
! 57: #define SAB_RBCL 0x2a /* r: rx byte count low */
! 58: #define SAB_TBCL 0x2a /* w: tx byte count low */
! 59: #define SAB_RBCH 0x2b /* r: rx byte count high */
! 60: #define SAB_XBCH 0x2b /* w: tx byte count high */
! 61: #define SAB_CCR0 0x2c /* rw: channel configuration register 0 */
! 62: #define SAB_CCR1 0x2d /* rw: channel configuration register 1 */
! 63: #define SAB_CCR2 0x2e /* rw: channel configuration register 2 */
! 64: #define SAB_CCR3 0x2f /* rw: channel configuration register 3 */
! 65: #define SAB_TSAX 0x30 /* w: time-slot assignment register tx */
! 66: #define SAB_TSAR 0x31 /* w: time-slot assignment register rx */
! 67: #define SAB_XCCR 0x32 /* w: tx channel capacity register */
! 68: #define SAB_RCCR 0x33 /* w: receive channel capacity register */
! 69: #define SAB_VSTR 0x34 /* r: version status */
! 70: #define SAB_BGR 0x34 /* w: baud rate generator */
! 71: #define SAB_TIC 0x35 /* w: transmit immediate character */
! 72: #define SAB_MXN 0x36 /* w: mask xon character */
! 73: #define SAB_MXF 0x37 /* w: mask xoff character */
! 74: #define SAB_GIS 0x38 /* r: global interrupt status */
! 75: #define SAB_IVA 0x38 /* w: interrupt vector address */
! 76: #define SAB_IPC 0x39 /* rw: interrupt port configuration */
! 77: #define SAB_ISR0 0x3a /* r: interrupt status 0 */
! 78: #define SAB_IMR0 0x3a /* w: interrupt mask 0 */
! 79: #define SAB_ISR1 0x3b /* r: interrupt status 1 */
! 80: #define SAB_IMR1 0x3b /* w: interrupt mask 1 */
! 81: #define SAB_PVR 0x3c /* rw: port value register */
! 82: #define SAB_PIS 0x3d /* r: port interrupt status */
! 83: #define SAB_PIM 0x3d /* w: port interrupt mask */
! 84: #define SAB_PCR 0x3e /* w: port configuration register */
! 85: #define SAB_CCR4 0x3f /* rw: channel configuration register 4 */
! 86:
! 87: /* SAB_STAR: status register */
! 88: #define SAB_STAR_XDOV 0x80 /* transmit data overflow */
! 89: #define SAB_STAR_XFW 0x40 /* transmit fifo write enable */
! 90: #define SAB_STAR_RFNE 0x20 /* rfifo not empty */
! 91: #define SAB_STAR_FCS 0x10 /* flow control status */
! 92: #define SAB_STAR_TEC 0x08 /* tx immediate char is executing */
! 93: #define SAB_STAR_CEC 0x04 /* command is executing */
! 94: #define SAB_STAR_CTS 0x02 /* cts status: 0:inactive/high,1:active/low */
! 95:
! 96: /* SAB_CMDR: command register */
! 97: #define SAB_CMDR_RMC 0x80 /* receive message complete */
! 98: #define SAB_CMDR_RRES 0x40 /* receiver reset */
! 99: #define SAB_CMDR_RFRD 0x20 /* receive fifo read enable */
! 100: #define SAB_CMDR_STI 0x10 /* start timer */
! 101: #define SAB_CMDR_XF 0x08 /* transmit frame */
! 102: #define SAB_CMDR_XRES 0x01 /* transmit reset */
! 103:
! 104: /* SAB_MODE: mode register */
! 105: #define SAB_MODE_FRTS 0x40 /* flow control using rts */
! 106: #define SAB_MODE_FCTS 0x20 /* flow control using cts */
! 107: #define SAB_MODE_FLON 0x10 /* flow control on */
! 108: #define SAB_MODE_RAC 0x08 /* receiver active */
! 109: #define SAB_MODE_RTS 0x04 /* request to send */
! 110: #define SAB_MODE_TRS 0x02 /* timer resolution */
! 111: #define SAB_MODE_TLP 0x01 /* test loop */
! 112:
! 113: /* SAB_TIMR: timer register */
! 114: #define SAB_TIMR_CNT 0xe0 /* count mask */
! 115: #define SAB_TIMR_VAL 0x1f /* value mask */
! 116:
! 117: /* SAB_DAFO: data format */
! 118: #define SAB_DAFO_XBRK 0x40 /* transmit break */
! 119: #define SAB_DAFO_STOP 0x20 /* stop bit: 0:1 bit, 1:2 bits */
! 120: #define SAB_DAFO_PAR1 0x10 /* parity 1, see below */
! 121: #define SAB_DAFO_PAR0 0x08 /* parity 0, see below */
! 122: #define SAB_DAFO_PARE 0x04 /* parity enable */
! 123: #define SAB_DAFO_CHL1 0x02 /* character length 1, see below */
! 124: #define SAB_DAFO_CHL0 0x01 /* character length 0, see below */
! 125:
! 126: #define SAB_DAFO_CHL_CSIZE (SAB_DAFO_CHL1|SAB_DAFO_CHL0)
! 127: #define SAB_DAFO_CHL_CS5 (SAB_DAFO_CHL1|SAB_DAFO_CHL0)
! 128: #define SAB_DAFO_CHL_CS6 (SAB_DAFO_CHL1)
! 129: #define SAB_DAFO_CHL_CS7 (SAB_DAFO_CHL0)
! 130: #define SAB_DAFO_CHL_CS8 (0)
! 131:
! 132: #define SAB_DAFO_PARMASK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
! 133: #define SAB_DAFO_PAR_MARK (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
! 134: #define SAB_DAFO_PAR_EVEN (SAB_DAFO_PAR1|SAB_DAFO_PARE)
! 135: #define SAB_DAFO_PAR_ODD (SAB_DAFO_PAR0|SAB_DAFO_PARE)
! 136: #define SAB_DAFO_PAR_SPACE (SAB_DAFO_PARE)
! 137: #define SAB_DAFO_PAR_NONE (0)
! 138:
! 139: /* SAB_RFC: rfifo control register */
! 140: #define SAB_RFC_DPS 0x40 /* disable parity storage */
! 141: #define SAB_RFC_DXS 0x20 /* disable storage of xon/xoff characters */
! 142: #define SAB_RFC_RFDF 0x10 /* rfifo data format: 0 data,1 data+stat */
! 143: #define SAB_RFC_RFTH1 0x08 /* rfifo threshold level 1, see below */
! 144: #define SAB_RFC_RFTH0 0x04 /* rfifo threshold level 0, see below */
! 145: #define SAB_RFC_TCDE 0x01 /* termination character detection enable */
! 146:
! 147: #define SAB_RFC_RFTH_MASK (SAB_RFC_RFTH1|SAB_RFC_RFTH0)
! 148: #define SAB_RFC_RFTH_32CHAR (SAB_RFC_RFTH1|SAB_RFC_RFTH0)
! 149: #define SAB_RFC_RFTH_16CHAR (SAB_RFC_RFTH1)
! 150: #define SAB_RFC_RFTH_4CHAR (SAB_RFC_RFTH0)
! 151: #define SAB_RFC_RFTH_1CHAR (0)
! 152:
! 153: /* SAB_RBCH: received byte count high */
! 154: #define SAB_RBCH_DMA 0x80 /* read back of XBCH DMA bit */
! 155: #define SAB_RBCH_CAS 0x20 /* read back of XBCH CAS bit */
! 156: #define SAB_RBCH_CNT 0x0f /* ms 4 bits of rx byte count (not used) */
! 157:
! 158: /* SAB_XBCH: transmit byte count high */
! 159: #define SAB_XBCH_DMA 0x80 /* dma mode: 1:dma, 0:interrupt */
! 160: #define SAB_XBCH_CAS 0x20 /* carrier detect auto-start */
! 161: #define SAB_XBCH_XC 0x10 /* transmit continuously */
! 162: #define SAB_XBCH_CNT 0x0f /* ms 4 bits of tx byte count */
! 163:
! 164: /* SAB_CCR0: channel configuration register 0 */
! 165: #define SAB_CCR0_PU 0x80 /* 0:power-down, 1:power-up */
! 166: #define SAB_CCR0_MCE 0x40 /* master clock enable */
! 167: #define SAB_CCR0_SC2 0x10 /* serial port config 2, see below */
! 168: #define SAB_CCR0_SC1 0x08 /* serial port config 1, see below */
! 169: #define SAB_CCR0_SC0 0x04 /* serial port config 0, see below */
! 170: #define SAB_CCR0_SM1 0x02 /* serial mode 1, see below */
! 171: #define SAB_CCR0_SM0 0x01 /* serial mode 0, see below */
! 172:
! 173: #define SAB_CCR0_SC_MASK (SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0)
! 174: #define SAB_CCR0_SC_NRZ (0)
! 175: #define SAB_CCR0_SC_NRZI (SAB_CCR0_SC1)
! 176: #define SAB_CCR0_SC_FM0 (SAB_CCR0_SC2)
! 177: #define SAB_CCR0_SC_FM1 (SAB_CCR0_SC2|SAB_CCR0_SC0)
! 178: #define SAB_CCR0_SC_MANCHESTER (SAB_CCR0_SC2|SAB_CCR0_SC1)
! 179:
! 180: #define SAB_CCR0_SM_MASK (SAB_CCR0_SM1|SAB_CCR0_SM0)
! 181: #define SAB_CCR0_SM_DLC (0)
! 182: #define SAB_CCR0_SM_DLCLOOP (SAB_CCR0_SM0)
! 183: #define SAB_CCR0_SM_BISYNC (SAB_CCR0_SM1)
! 184: #define SAB_CCR0_SM_ASYNC (SAB_CCR0_SM1|SAB_CCR0_SM0)
! 185:
! 186: /* SAB_CCR1: channel configuration register 1 */
! 187: #define SAB_CCR1_ODS 0x10 /* Output driver select:1:pushpull,0:odrain */
! 188: #define SAB_CCR1_BCR 0x08 /* bit clock rate: 1:async, 0:isochronous */
! 189: #define SAB_CCR1_CM2 0x04 /* clock mode 2, see below */
! 190: #define SAB_CCR1_CM1 0x02 /* clock mode 1, see below */
! 191: #define SAB_CCR1_CM0 0x01 /* clock mode 0, see below */
! 192:
! 193: #define SAB_CCR1_CM_MASK (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
! 194: #define SAB_CCR1_CM_7 (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
! 195:
! 196: /* SAB_CCR2: channel configuration register 2, depends on clock mode above */
! 197: /* clock mode 0a, 1, 4, 5 */
! 198: #define SAB_CCR2_SOC1 0x80 /* special output 1, below */
! 199: #define SAB_CCR2_SOC0 0x40 /* special output 0, below */
! 200: #define SAB_CCR2_SOC_MASK (SAB_CCR2_SOC1|SAB_CCR2_SOC0)
! 201: #define SAB_CCR2_SOC_RTSHIGH (SAB_CCR2_SOC1)
! 202: #define SAB_CCR2_SOC_RTSNORM (0)
! 203: #define SAB_CCR2_SOC_RTSRX (SAB_CCR2_SOC1|SAB_CCR2_SOC0)
! 204: /* clock mode 0b, 2, 3, 6, 7 */
! 205: #define SAB_CCR2_BR9 0x80 /* baud rate bit 9 */
! 206: #define SAB_CCR2_BR8 0x40 /* baud rate bit 8 */
! 207: #define SAB_CCR2_BDF 0x20 /* baud rate division factor: 0:1: 1:BRG */
! 208: #define SAB_CCR2_SSEL 0x10 /* clock source select */
! 209: /* clock mode 5 */
! 210: #define SAB_CCR2_XCS0 0x20 /* tx clock shift, bit 0 */
! 211: #define SAB_CCR2_RCS0 0x10 /* rx clock shift, bit 0 */
! 212: /* clock mode 0b, 2, 3, 4, 5, 6, 7 */
! 213: #define SAB_CCR2_TOE 0x08 /* tx clock output enable */
! 214: /* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */
! 215: #define SAB_CCR2_RWX 0x04 /* read/write exchange (dma mode only) */
! 216: #define SAB_CCR2_DIV 0x01 /* data inversion (nrz) */
! 217:
! 218: /* SAB_CCR3: channel configuration register 3 (v2 or greater) */
! 219: #define SAB_CCR3_PSD 0x01 /* dpll phase shift disable (nrz/nrzi) */
! 220:
! 221: /* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */
! 222: #define SAB_TSAX_TSNX 0xfc /* time-slot number transmit */
! 223: #define SAB_TSAX_XCS2 0x02 /* transmit clock shift bit 2 */
! 224: #define SAB_TSAX_XCS1 0x01 /* transmit clock shift bit 1 */
! 225:
! 226: /* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */
! 227: #define SAB_TSAR_TSNR 0xfc /* time-slot number receive */
! 228: #define SAB_TSAR_RCS2 0x02 /* receive clock shift bit 2 */
! 229: #define SAB_TSAR_RCS1 0x01 /* receive clock shift bit 1 */
! 230:
! 231: /* SAB_VSTR: version status register */
! 232: #define SAB_VSTR_CD 0x80 /* carrier detect status */
! 233: #define SAB_VSTR_DPLA 0x40 /* dpll asynchronous */
! 234: #define SAB_VSTR_VMASK 0x0f /* chip version mask: */
! 235: #define SAB_VSTR_V_1 0x00 /* version 1 */
! 236: #define SAB_VSTR_V_2 0x01 /* version 2 */
! 237: #define SAB_VSTR_V_32 0x02 /* version 3.2 */
! 238:
! 239: /* SAB_GIS: global interrupt status register */
! 240: #define SAB_GIS_PI 0x80 /* universal port interrupt */
! 241: #define SAB_GIS_ISA1 0x08 /* interrupt status a1 */
! 242: #define SAB_GIS_ISA0 0x04 /* interrupt status a0 */
! 243: #define SAB_GIS_ISB1 0x02 /* interrupt status b1 */
! 244: #define SAB_GIS_ISB0 0x01 /* interrupt status b0 */
! 245:
! 246: /* SAB_IVA: interrupt vector address */
! 247: #define SAB_IVA_MASK 0xf8 /* interrupt vector address mask */
! 248:
! 249: /* SAB_IPC: interrupt port configuration */
! 250: #define SAB_IPC_VIS 0x80 /* masked interrupt bits visible */
! 251: #define SAB_IPC_SLAMASK 0x18 /* slave address mask */
! 252: #define SAB_IPC_CASM 0x04 /* cascading mode */
! 253: #define SAB_IPC_ICMASK 0x03 /* port config mask: */
! 254: #define SAB_IPC_ICOD 0x00 /* open drain output */
! 255: #define SAB_IPC_ICPL 0x01 /* push/pull active low output */
! 256: #define SAB_IPC_ICPH 0x03 /* push/pull active high output */
! 257:
! 258: /* SAB_ISR0: interrupt status 0 */
! 259: #define SAB_ISR0_TCD 0x80 /* termination character detected */
! 260: #define SAB_ISR0_TIME 0x40 /* time-out limit exceeded */
! 261: #define SAB_ISR0_PERR 0x20 /* parity error */
! 262: #define SAB_ISR0_FERR 0x10 /* framing error */
! 263: #define SAB_ISR0_PLLA 0x08 /* dpll asynchronous */
! 264: #define SAB_ISR0_CDSC 0x04 /* carrier detect status change */
! 265: #define SAB_ISR0_RFO 0x02 /* rfifo overflow */
! 266: #define SAB_ISR0_RPF 0x01 /* receive pool full */
! 267:
! 268: /* SAB_ISR1: interrupt status 1 */
! 269: #define SAB_ISR1_BRK 0x80 /* break detected */
! 270: #define SAB_ISR1_BRKT 0x40 /* break terminated */
! 271: #define SAB_ISR1_ALLS 0x20 /* all sent */
! 272: #define SAB_ISR1_XOFF 0x10 /* xoff detected */
! 273: #define SAB_ISR1_TIN 0x08 /* timer interrupt */
! 274: #define SAB_ISR1_CSC 0x04 /* clear to send status change */
! 275: #define SAB_ISR1_XON 0x02 /* xon detected */
! 276: #define SAB_ISR1_XPR 0x01 /* transmit pool ready */
! 277:
! 278: /* SAB_IMR0: interrupt mask 0 */
! 279: #define SAB_IMR0_TCD 0x80 /* termination character detected */
! 280: #define SAB_IMR0_TIME 0x40 /* time-out limit exceeded */
! 281: #define SAB_IMR0_PERR 0x20 /* parity error */
! 282: #define SAB_IMR0_FERR 0x10 /* framing error */
! 283: #define SAB_IMR0_PLLA 0x08 /* dpll asynchronous */
! 284: #define SAB_IMR0_CDSC 0x04 /* carrier detect status change */
! 285: #define SAB_IMR0_RFO 0x02 /* rfifo overflow */
! 286: #define SAB_IMR0_RPF 0x01 /* receive pool full */
! 287:
! 288: /* SAB_ISR1: interrupt mask 1 */
! 289: #define SAB_IMR1_BRK 0x80 /* break detected */
! 290: #define SAB_IMR1_BRKT 0x40 /* break terminated */
! 291: #define SAB_IMR1_ALLS 0x20 /* all sent */
! 292: #define SAB_IMR1_XDU 0x10 /* xoff detected */
! 293: #define SAB_IMR1_TIN 0x08 /* timer interrupt */
! 294: #define SAB_IMR1_CSC 0x04 /* clear to send status change */
! 295: #define SAB_IMR1_XMR 0x02 /* xon detected */
! 296: #define SAB_IMR1_XPR 0x01 /* transmit pool ready */
! 297:
! 298: /* SAB_PVR: port value register */
! 299: #define SAB_PVR_DSR_A 0x01 /* port A DSR */
! 300: #define SAB_PVR_DTR_A 0x02 /* port A DTR */
! 301: #define SAB_PVR_DTR_B 0x04 /* port B DTR */
! 302: #define SAB_PVR_DSR_B 0x08 /* port B DSR */
! 303: #define SAB_PVR_MAGIC 0x10 /* dunno... */
! 304:
! 305: /* SAB_CCR4: channel configuration register 4 */
! 306: #define SAB_CCR4_MCK4 0x80 /* master clock divide by 4 */
! 307: #define SAB_CCR4_EBRG 0x40 /* enhanced baud rate generator mode */
! 308: #define SAB_CCR4_TST1 0x20 /* test pin */
! 309: #define SAB_CCR4_ICD 0x10 /* invert polarity of carrier detect */
! 310:
! 311: /* Receive status byte */
! 312: #define SAB_RSTAT_PE 0x80 /* parity error */
! 313: #define SAB_RSTAT_FE 0x40 /* framing error */
! 314: #define SAB_RSTAT_PAR 0x01 /* parity bit */
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