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File: [local] / sys / dev / ic / apcdmareg.h (download)
Revision 1.1.1.1 (vendor branch), Tue Mar 4 16:10:15 2008 UTC (16 years, 6 months ago) by nbrk
Import of OpenBSD 4.2 release kernel tree with initial code to support Jornada 720/728, StrongARM 1110-based handheld PC. At this point kernel roots on NFS and boots into vfs_mountroot() and traps. What is supported: - glass console, Jornada framebuffer (jfb) works in 16bpp direct color mode (needs some palette tweaks for non black/white/blue colors, i think) - saic, SA11x0 interrupt controller (needs cleanup) - sacom, SA11x0 UART (supported only as boot console for now) - SA11x0 GPIO controller fully supported (but can't handle multiple interrupt handlers on one gpio pin) - sassp, SSP port on SA11x0 that attaches spibus - Jornada microcontroller (jmcu) to control kbd, battery, etc throught the SPI bus (wskbd attaches on jmcu, but not tested) - tod functions seem work - initial code for SA-1111 (chip companion) : this is TODO Next important steps, i think: - gpio and intc on sa1111 - pcmcia support for sa11x0 (and sa1111 help logic) - REAL root on nfs when we have PCMCIA support (we may use any of supported pccard NICs) - root on wd0! (using already supported PCMCIA-ATA) |
/* $OpenBSD: apcdmareg.h,v 1.2 2003/06/02 18:53:18 jason Exp $ */ /* * Copyright (c) 2001 Jason L. Wright (jason@thought.net) * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * Definitions for Sun APC DMA controller. */ /* APC DMA registers */ #define APC_CSR 0x0010 /* control/status */ #define APC_CVA 0x0020 /* capture virtual address */ #define APC_CC 0x0024 /* capture count */ #define APC_CNVA 0x0028 /* capture next virtual address */ #define APC_CNC 0x002c /* capture next count */ #define APC_PVA 0x0030 /* playback virtual address */ #define APC_PC 0x0034 /* playback count */ #define APC_PNVA 0x0038 /* playback next virtual address */ #define APC_PNC 0x003c /* playback next count */ /* * APC DMA Register definitions */ #define APC_CSR_RESET 0x00000001 /* reset */ #define APC_CSR_CDMA_GO 0x00000004 /* capture dma go */ #define APC_CSR_PDMA_GO 0x00000008 /* playback dma go */ #define APC_CSR_CODEC_RESET 0x00000020 /* codec reset */ #define APC_CSR_CPAUSE 0x00000040 /* capture dma pause */ #define APC_CSR_PPAUSE 0x00000080 /* playback dma pause */ #define APC_CSR_CMIE 0x00000100 /* capture pipe empty enb */ #define APC_CSR_CMI 0x00000200 /* capture pipe empty intr */ #define APC_CSR_CD 0x00000400 /* capture nva dirty */ #define APC_CSR_CM 0x00000800 /* capture data lost */ #define APC_CSR_PMIE 0x00001000 /* pb pipe empty intr enable */ #define APC_CSR_PD 0x00002000 /* pb nva dirty */ #define APC_CSR_PM 0x00004000 /* pb pipe empty */ #define APC_CSR_PMI 0x00008000 /* pb pipe empty interrupt */ #define APC_CSR_EIE 0x00010000 /* error interrupt enable */ #define APC_CSR_CIE 0x00020000 /* capture intr enable */ #define APC_CSR_PIE 0x00040000 /* playback intr enable */ #define APC_CSR_GIE 0x00080000 /* general intr enable */ #define APC_CSR_EI 0x00100000 /* error interrupt */ #define APC_CSR_CI 0x00200000 /* capture interrupt */ #define APC_CSR_PI 0x00400000 /* playback interrupt */ #define APC_CSR_GI 0x00800000 /* general interrupt */ #define APC_CSR_PLAY ( \ APC_CSR_EI | \ APC_CSR_GIE | \ APC_CSR_PIE | \ APC_CSR_EIE | \ APC_CSR_PDMA_GO | \ APC_CSR_PMIE ) #define APC_CSR_CAPTURE ( \ APC_CSR_EI | \ APC_CSR_GIE | \ APC_CSR_CIE | \ APC_CSR_EIE | \ APC_CSR_CDMA_GO ) #define APC_CSR_PLAY_PAUSE (~( \ APC_CSR_PPAUSE | \ APC_CSR_GI | \ APC_CSR_PI | \ APC_CSR_CI | \ APC_CSR_EI | \ APC_CSR_PMI | \ APC_CSR_PMIE | \ APC_CSR_CMI | \ APC_CSR_CMIE ) ) #define APC_CSR_CAPTURE_PAUSE (~( \ APC_CSR_PPAUSE | \ APC_CSR_GI | \ APC_CSR_PI | \ APC_CSR_CI | \ APC_CSR_EI | \ APC_CSR_PMI | \ APC_CSR_PMIE | \ APC_CSR_CMI | \ APC_CSR_CMIE ) ) #define APC_CSR_INTR_MASK ( \ APC_CSR_GI | \ APC_CSR_PI | \ APC_CSR_CI | \ APC_CSR_EI | \ APC_CSR_PMI | \ APC_CSR_CMI )