Annotation of sys/dev/ic/i82802reg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: i82802reg.h,v 1.3 2003/10/21 18:58:49 jmc Exp $ */
2:
3: /*
4: * Copyright (c) 2000 Michael Shalayeff
5: * All rights reserved.
6: *
7: * Redistribution and use in source and binary forms, with or without
8: * modification, are permitted provided that the following conditions
9: * are met:
10: * 1. Redistributions of source code must retain the above copyright
11: * notice, this list of conditions and the following disclaimer.
12: * 2. Redistributions in binary form must reproduce the above copyright
13: * notice, this list of conditions and the following disclaimer in the
14: * documentation and/or other materials provided with the distribution.
15: *
16: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17: * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18: * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19: * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20: * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21: * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22: * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24: * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25: * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26: * THE POSSIBILITY OF SUCH DAMAGE.
27: */
28:
29: /*
30: * Intel 82802AB/82802AC Firmware Hub
31: *
32: * see: ftp://download.intel.com/design/chipsets/datashts/29065802.pdf
33: * and http://developer.intel.com/design/chipsets/manuals/298029.pdf
34: */
35:
36: /*
37: * unfortunately FWH does not show up in the pci device scan, 10x intel.
38: * so all we do is probe for it in the pchb driver at the following address.
39: */
40: #define I82802_IOBASE 0xffb00000
41: #define I82802_IOSIZE 0x00100000
42:
43: /*
44: * FWH registers
45: * (table 4-4)
46: */
47: #define I82802_BLOCK_LK 0xf0002
48: #define I82802_MINUS01_LK 0xe0002
49: #define I82802_MINUS02_LK 0xd0002
50: #define I82802_MINUS03_LK 0xc0002
51: #define I82802_MINUS04_LK 0xb0002
52: #define I82802_MINUS05_LK 0xa0002
53: #define I82802_MINUS06_LK 0x90002
54: #define I82802_MINUS07_LK 0x80002
55: #define I82802_MINUS08_LK 0x70002
56: #define I82802_MINUS09_LK 0x60002
57: #define I82802_MINUS10_LK 0x50002
58: #define I82802_MINUS11_LK 0x40002
59: #define I82802_MINUS12_LK 0x30002
60: #define I82802_MINUS13_LK 0x20002
61: #define I82802_MINUS14_LK 0x10002
62: #define I82802_MINUS15_LK 0x00002
63: #define I82802_FGPI_REG 0xc0100
64:
65: /*
66: * T_BLOCK_LK and T_MINUS_* (block locking registers)
67: * (table 4-5)
68: */
69: #define I82802_BLR_RD 0x04
70: #define I82802_BLR_LD 0x02
71: #define I82802_BLR_WL 0x01
72:
73: /*
74: * Register Based Locking Value Definitions
75: * (tabe 4-6)
76: */
77: #define I82802_LV_FULL 0x00
78: #define I82802_LV_WRITE 0x01
79: #define I82802_LV_DOWN 0x02
80: #define I82802_LV_READ 0x04
81:
82: /*
83: * General Purpose Inputs Register
84: * (table 4-7)
85: */
86: #define I82802_FGPI_PIN4 0x10 /* PLCC-30/T SOP-7 */
87: #define I82802_FGPI_PIN3 0x08 /* PLCC-30/T SOP-15 */
88: #define I82802_FGPI_PIN2 0x04 /* PLCC-30/T SOP-16 */
89: #define I82802_FGPI_PIN1 0x02 /* PLCC-30/T SOP-17 */
90: #define I82802_FGPI_PIN0 0x01 /* PLCC-30/T SOP-18 */
91:
92: /*
93: * RNG registers
94: */
95: #define I82802_RNG_HWST 0xc015f
96: #define I82802_RNG_HWST_PRESENT 0x40
97: #define I82802_RNG_HWST_ENABLE 0x01
98: #define I82802_RNG_RNGST 0xc0160
99: #define I82802_RNG_RNGST_DATAV 0x01
100: #define I82802_RNG_DATA 0xc0161
101:
CVSweb