Annotation of sys/dev/ic/silireg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: silireg.h,v 1.20 2007/04/07 13:02:52 pascoe Exp $ */
2:
3: /*
4: * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
5: *
6: * Permission to use, copy, modify, and distribute this software for any
7: * purpose with or without fee is hereby granted, provided that the above
8: * copyright notice and this permission notice appear in all copies.
9: *
10: * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11: * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12: * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13: * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14: * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15: * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16: * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17: */
18:
19: /* PCI Registers */
20: #define SILI_PCI_BAR_GLOBAL 0x10 /* Global Registers address */
21: #define SILI_PCI_BAR_PORT 0x18 /* Port Registers address */
22: #define SILI_PCI_BAR_INDIRECT 0x20 /* Indirect IO Registers address */
23:
24: /* Global Registers */
25: #define SILI_REG_PORT0_STATUS 0x00 /* Port 0 Slot Status */
26: #define SILI_REG_PORT1_STATUS 0x04 /* Port 1 Slot Status */
27: #define SILI_REG_PORT2_STATUS 0x08 /* Port 2 Slot Status */
28: #define SILI_REG_PORT3_STATUS 0x0c /* Port 3 Slot Status */
29: #define SILI_REG_GC 0x40 /* Global Control */
30: #define SILI_REG_GC_GR (1<<31) /* Global Reset */
31: #define SILI_REG_GC_MSIACK (1<<30) /* MSI Acknowledge */
32: #define SILI_REG_GC_I2CINT (1<<29) /* I2C Interrupt Enable */
33: #define SILI_REG_GC_PERRDIS (1<<28) /* PCI Error Report Disable */
34: #define SILI_REG_GC_REQ64 (1<<20) /* latched PCI REQ64 */
35: #define SILI_REG_GC_DEVSEL (1<<19) /* latched PCI DEVSEL */
36: #define SILI_REG_GC_STOP (1<<18) /* latched PCI STOP */
37: #define SILI_REG_GC_TRDY (1<<17) /* latched PCI TRDY */
38: #define SILI_REG_GC_M66EN (1<<16) /* M66EN PCI bus signal */
39: #define SILI_REG_GC_PIE_MASK 0x0f
40: #define SILI_FMT_GC "\020" "\040GR" "\037MSIACK" "\036I2CINT" \
41: "\035PERRDIS" "\025REQ64" "\024DEVSEL" \
42: "\023STOP" "\022TRDY" "\021M66EN" \
43: "\004P3IE" "\003P2IE" "\002P1IE" "\001P0IE"
44: #define SILI_REG_GIS 0x44 /* Global Interrupt Status */
45: #define SILI_REG_GIS_I2C (1 << 29)
46: #define SILI_REG_GIS_PIS_MASK 0x0f
47: #define SILI_REG_PHYCONF 0x48 /* PHY Configuration */
48: #define SILI_REG_BISTCTL 0x50 /* BIST Control */
49: #define SILI_REG_BISTPATTERN 0x54 /* BIST Pattern */
50: #define SILI_REG_BISTSTAT 0x58 /* BIST Status */
51: #define SILI_REG_FLASHADDR 0x70 /* Flash Address */
52: #define SILI_REG_FLASHDATA 0x74 /* Flash Memory Data / GPIO Control */
53: #define SILI_REG_GPIOCTL SILI_REG_FLASHDATA
54: #define SILI_REG_IICADDR 0x78 /* I2C Address */
55: #define SILI_REG_IIC 0x7c /* I2C Data / Control */
56:
57: #define SILI_PORT_SIZE 0x2000
58: #define SILI_PORT_OFFSET(_p) ((_p) * SILI_PORT_SIZE)
59:
60: /* Port Registers */
61: #define SILI_PREG_LRAM 0x0000 /* Port LRAM */
62: #define SILI_PREG_SLOT_WIDTH 0x80
63: #define SILI_PREG_SLOT(_s) (SILI_PREG_LRAM + (_s) * SILI_PREG_SLOT_WIDTH)
64: #define SILI_PREG_RX_COUNT(_s) (SILI_PREG_SLOT(_s) + 0x04)
65: #define SILI_PREG_SIG_HI(_s) (SILI_PREG_SLOT(_s) + 0x0c)
66: #define SILI_PREG_SIG_HI_SHIFT 8
67: #define SILI_PREG_SIG_LO(_s) (SILI_PREG_SLOT(_s) + 0x14)
68: #define SILI_PREG_SIG_LO_MASK 0xff
69: /* XXX PMP Bits */
70: #define SILI_PREG_PCS 0x1000 /* Port Control Set / Status */
71: #define SILI_PREG_PCS_PORTRDY (1<<31) /* Port Ready */
72: #define SILI_PREG_PCS_OOBB (1<<25) /* OOB Bypass */
73: #define SILI_PREG_PCS_ACTIVE(_x) (((_x)>>16) & 0x1f) /* Active Slot */
74: #define SILI_PREG_PCS_LED_ON (1<<15) /* LED On */
75: #define SILI_PREG_PCS_AIA (1<<14) /* Auto Interlock Accept */
76: #define SILI_PREG_PCS_PMEN (1<<13) /* Port Mult Enable */
77: #define SILI_PREG_PCS_IA (1<<12) /* Interlock Accept */
78: #define SILI_PREG_PCS_IR (1<<11) /* Interlock Reject */
79: #define SILI_PREG_PCS_A32B (1<<10) /* 32-bit Activation */
80: #define SILI_PREG_PCS_SD (1<<9) /* Scrambler Disable */
81: #define SILI_PREG_PCS_CD (1<<8) /* CONT Disable */
82: #define SILI_PREG_PCS_TB (1<<7) /* Transmit BIST */
83: #define SILI_PREG_PCS_RESUME (1<<6) /* Resume */
84: #define SILI_PREG_PCS_PLEN (1<<5) /* Packet Length */
85: #define SILI_PREG_PCS_LEDDISABLE (1<<4) /* LED Disable */
86: #define SILI_PREG_PCS_NOINTCLR (1<<3) /* No Intr Clear on Read */
87: #define SILI_PREG_PCS_PORTINIT (1<<2) /* Port Initialize */
88: #define SILI_PREG_PCS_DEVRESET (1<<1) /* Device Reset */
89: #define SILI_PREG_PCS_PORTRESET (1<<0) /* Port Reset */
90: #define SILI_PFMT_PCS "\020" "\032OOBB" "\020LED_ON" "\017AIA" \
91: "\016PMEN" "\015IA" "\014IR" "\013A32B" \
92: "\012SD" "\011CD" "\010TB" "\007RESUME" \
93: "\006PLEN" "\005LEDDISABLE" \
94: "\004NOINTCLR" "\003PORTINIT" \
95: "\002PORTINIT" "\001PORTRESET"
96: #define SILI_PREG_PCC 0x1004 /* Port Control Clear */
97: #define SILI_PREG_PCC_OOBB (1<<25) /* OOB Bypass */
98: #define SILI_PREG_PCC_LED_ON (1<<15) /* LED On */
99: #define SILI_PREG_PCC_AIA (1<<14) /* Auto Interlock Accept */
100: #define SILI_PREG_PCC_PMEN (1<<13) /* Port Mult Enable */
101: #define SILI_PREG_PCC_IA (1<<12) /* Interlock Accept */
102: #define SILI_PREG_PCC_IR (1<<11) /* Interlock Reject */
103: #define SILI_PREG_PCC_A32B (1<<10) /* 32-bit Activation */
104: #define SILI_PREG_PCC_SD (1<<9) /* Scrambler Disable */
105: #define SILI_PREG_PCC_CD (1<<8) /* CONT Disable */
106: #define SILI_PREG_PCC_TB (1<<7) /* Transmit BIST */
107: #define SILI_PREG_PCC_RESUME (1<<6) /* Resume */
108: #define SILI_PREG_PCC_PLEN (1<<5) /* Packet Length */
109: #define SILI_PREG_PCC_LEDDISABLE (1<<4) /* LED Disable */
110: #define SILI_PREG_PCC_NOINTCLR (1<<3) /* No Intr Clear on Read */
111: #define SILI_PREG_PCC_PORTINIT (1<<2) /* Port Initialize */
112: #define SILI_PREG_PCC_DEVRESET (1<<1) /* Device Reset */
113: #define SILI_PREG_PCC_PORTRESET (1<<0) /* Port Reset */
114: #define SILI_PREG_IS 0x1008 /* Interrupt Status */
115: #define SILI_PREG_IS_SDB (1<<11) /* SDB Notify */
116: #define SILI_PREG_IS_HANDSHAKE (1<<10) /* Handshake error threshold */
117: #define SILI_PREG_IS_CRC (1<<9) /* CRC error threshold */
118: #define SILI_PREG_IS_DEC (1<<8) /* 8b/10b decode error thresh */
119: #define SILI_PREG_IS_DEVXCHG (1<<7) /* Device Exchanged */
120: #define SILI_PREG_IS_UNRECFIS (1<<6) /* Unrecognized FIS Type */
121: #define SILI_PREG_IS_COMWAKE (1<<5) /* ComWake */
122: #define SILI_PREG_IS_PHYRDYCHG (1<<4) /* Phy Ready Change */
123: #define SILI_PREG_IS_PMCHG (1<<3) /* Power Mmgt Change */
124: #define SILI_PREG_IS_PORTRDY (1<<2) /* Port Ready */
125: #define SILI_PREG_IS_CMDERR (1<<1) /* Command Error */
126: #define SILI_PREG_IS_CMDCOMP (1<<0) /* Command Completion */
127: #define SILI_PFMT_IS "\020" "\014SDB" "\013HANDSHAKE" \
128: "\012CRC" "\011DECODE" \
129: "\010DEVXCHG" "\007UNRECFIS" \
130: "\006COMWAKE" "\005PHYRDYCHG" \
131: "\004PMCHG" "\003PORTRDY" \
132: "\002CMDERR" "\001CMDCOMP"
133: #define SILI_PREG_IES 0x1010 /* Interrupt Enable Set */
134: #define SILI_PREG_IEC 0x1014 /* Interrupt Enable Clear */
135: #define SILI_PREG_IE_SDB (1<<11) /* SDB Notify */
136: #define SILI_PREG_IE_DEVXCHG (1<<7) /* Device Exchange */
137: #define SILI_PREG_IE_UNRECFIS (1<<6) /* Unrecognized FIS Type */
138: #define SILI_PREG_IE_COMWAKE (1<<5) /* ComWake */
139: #define SILI_PREG_IE_PHYRDYCHG (1<<4) /* Phy Ready Change */
140: #define SILI_PREG_IE_PMCHG (1<<3) /* Power Mmgt Change */
141: #define SILI_PREG_IE_PORTRDY (1<<2) /* Port Ready */
142: #define SILI_PREG_IE_CMDERR (1<<1) /* Command Error */
143: #define SILI_PREG_IE_CMDCOMP (1<<0) /* Command Completion */
144: #define SILI_PREG_IE_ALL 0x08ff
145: #define SILI_PREG_AUA 0x101c /* Activation Upper Address */
146: #define SILI_PREG_FIFO 0x1020 /* Command Execution FIFO */
147: #define SILI_PREG_CE 0x1024 /* Command Error */
148: #define SILI_PREG_CE_DEVICEERROR 1
149: #define SILI_PREG_CE_SDBERROR 2
150: #define SILI_PREG_CE_DATAFISERROR 3
151: #define SILI_PREG_FC 0x1028 /* FIS Configuration */
152: #define SILI_PREG_RFT 0x102c /* Request FIFO Threshold */
153: #define SILI_PREG_DEC 0x1040 /* 8b/10b Decode Error Counter */
154: #define SILI_PREG_CEC 0x1044 /* CRC Error Counter */
155: #define SILI_PREG_HEC 0x1048 /* Handshake Error Counter */
156: #define SILI_PREG_PHYCONF 0x1050 /* Port PHY Configuration */
157: #define SILI_PREG_PSS 0x1800 /* Port Slot Status */
158: #define SILI_PREG_PSS_ATTENTION (1 << 31)
159: #define SILI_PREG_PSS_ALL_SLOTS 0x7fffffff
160: #define SILI_PREG_CAR_LO(_s) (0x1c00 + ((_s) * 0x8)) /* Cmd Activate Reg */
161: #define SILI_PREG_CAR_HI(_s) (0x1c00 + ((_s) * 0x8) + 0x4)
162: #define SILI_PREG_CONTEXT 0x1e0f /* Port Context Register */
163: #define SILI_PREG_SCTL 0x1f00 /* SControl */
164: #define SILI_PREG_SSTS 0x1f04 /* SStatus */
165: #define SILI_PREG_SERR 0x1f08 /* SError */
166: #define SILI_PREG_SACT 0x1f0c /* SActive */
167:
168:
169: struct sili_sge {
170: u_int32_t addr_lo;
171: u_int32_t addr_hi;
172: u_int32_t data_count;
173: u_int32_t flags;
174: #define SILI_SGE_TRM (1<<31)
175: #define SILI_SGE_LNK (1<<30)
176: #define SILI_SGE_DRD (1<<29)
177: #define SILI_SGE_XCF (1<<28)
178: } __packed;
179:
180: #define SILI_SGT_SGLLEN 4
181:
182: struct sili_sgt {
183: struct sili_sge sgl[SILI_SGT_SGLLEN];
184: } __packed;
185:
186: #define SILI_PRB_PROTOCOL_OVERRIDE (1<<0)
187: #define SILI_PRB_RETRANSMIT (1<<1)
188: #define SILI_PRB_EXTERNAL_COMMAND (1<<2)
189: #define SILI_PRB_RECEIVE (1<<3)
190: #define SILI_PRB_PACKET_READ (1<<4)
191: #define SILI_PRB_PACKET_WRITE (1<<5)
192: #define SILI_PRB_INTERRUPT_MASK (1<<6)
193: #define SILI_PRB_SOFT_RESET (1<<7)
194:
195: struct sili_prb { /* this is just a useful template */
196: u_int16_t control;
197: u_int16_t reserved1;
198: u_int32_t reserved2;
199:
200: u_int8_t fis[ATA_FIS_LENGTH];
201:
202: u_int32_t reserved3[9];
203: } __packed;
204:
205: struct sili_prb_ata {
206: u_int16_t control;
207: u_int16_t protocol_override;
208: u_int32_t rx_count;
209:
210: u_int8_t fis[ATA_FIS_LENGTH];
211:
212: u_int32_t reserved;
213:
214: struct sili_sge sgl[2];
215: } __packed;
216:
217: struct sili_prb_packet {
218: u_int16_t control;
219: u_int16_t protocol_override;
220: u_int32_t rx_count;
221:
222: u_int8_t fis[ATA_FIS_LENGTH];
223:
224: u_int32_t reserved;
225:
226: u_int8_t cdb[16];
227:
228: struct sili_sge sgl[1];
229: } __packed;
230:
231: struct sili_prb_softreset {
232: u_int16_t control;
233: u_int16_t reserved1;
234: u_int32_t reserved2;
235:
236: u_int8_t fis[ATA_FIS_LENGTH];
237:
238: u_int32_t reserved3[9];
239: } __packed;
240:
241: #define SILI_MAX_CMDS 31
242: #define SILI_PRB_LENGTH 64
243: #define SILI_PRB_ALIGN 8
244: #define SILI_SGT_LENGTH 64
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