Annotation of sys/dev/mii/tqphyreg.h, Revision 1.1.1.1
1.1 nbrk 1: /* $OpenBSD: tqphyreg.h,v 1.2 2002/05/04 11:30:06 fgsch Exp $ */
2: /* $NetBSD: tqphyreg.h,v 1.2 1999/09/16 05:58:18 soren Exp $ */
3:
4: /*
5: * Copyright (c) 1999 Soren S. Jorvang.
6: * All rights reserved.
7: *
8: * Redistribution and use in source and binary forms, with or without
9: * modification, are permitted provided that the following conditions
10: * are met:
11: * 1. Redistributions of source code must retain the above copyright
12: * notice, this list of conditions, and the following disclaimer.
13: * 2. Redistributions in binary form must reproduce the above copyright
14: * notice, this list of conditions and the following disclaimer in the
15: * documentation and/or other materials provided with the distribution.
16: *
17: * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18: * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19: * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20: * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21: * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22: * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23: * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24: * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25: * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26: * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27: * SUCH DAMAGE.
28: */
29:
30: #ifndef _DEV_MII_TQPHYREG_H_
31: #define _DEV_MII_TQPHYREG_H_
32:
33: /*
34: * TDK TSC78Q2120 PHY registers
35: *
36: * Documentation available at http://www.tsc.tdk.com/lan/78Q2120.pdf .
37: */
38:
39: /*
40: * http://cesdis.gsfc.nasa.gov/linux/misc/100mbps.html has this to say:
41: *
42: * TDK Semiconductor (formerly Silicon Systems) 78Q2120 (10/100) and 78Q2121
43: * (100Mbps only) MII transceivers. The first PHY available which worked at
44: * both 5.0 and 3.3V. Used on the 3Com 3c574 and Ositech products. The OUI
45: * is 00:c0:39, models 20 and 21. Warning: The older revision 3 part has
46: * several bugs. It always responds to MDIO address 0, and has clear-only
47: * semantics for the capability-advertise registers. The current (3/99)
48: * revision 11 part, shipping since 8/98, has reportedly fixed these problems.
49: */
50:
51: #define MII_TQPHY_VENDOR 0x10 /* Vendor specific register */
52: #define VENDOR_RPTR 0x8000 /* Repeater mode */
53: #define VENDOR_INTLEVEL 0x4000 /* INTR pin level */
54: #define VENDOR_RSVD1 0x2000 /* Reserved */
55: #define VENDOR_TXHIM 0x1000 /* Transmit high impedance */
56: #define VENDOR_SEQTESTINHIBIT 0x0800 /* Disables 10baseT SQE testing */
57: #define VENDOR_10BT_LOOPBACK 0x0400 /* 10baseT natural loopback */
58: #define VENDOR_GPIO1_DAT 0x0200 /* General purpose I/O 1 data */
59: #define VENDOR_GPIO1_DIR 0x0100 /* General purpose I/O 1 direction */
60: #define VENDOR_GPIO0_DAT 0x0080 /* General purpose I/O 0 data */
61: #define VENDOR_GPIO0_DIR 0x0040 /* General purpose I/O 0 direction */
62: #define VENDOR_APOL 0x0020 /* Auto polarity */
63: #define VENDOR_RVSPOL 0x0010 /* Reverse polarity */
64: #define VENDOR_RSVD2 0x0008 /* Reserved (must be zero) */
65: #define VENDOR_RSVD3 0x0004 /* Reserved (must be zero) */
66: #define VENDOR_PCSBP 0x0002 /* PCS bypass */
67: #define VENDOR_RXCC 0x0001 /* Receive clock control */
68:
69: #define MII_TQPHY_INTR 0x11 /* Interrupt control/status register */
70: #define INTR_JABBER_IE 0x8000 /* Jabber interrupt enable */
71: #define INTR_RXER_IE 0x4000 /* Receive error enable */
72: #define INTR_PRX_IE 0x2000 /* Page received enable */
73: #define INTR_PFD_IE 0x1000 /* Parallel detect fault enable */
74: #define INTR_LPACK_IE 0x0800 /* Link partner ack. enable */
75: #define INTR_LSCHG_IE 0x0400 /* Link status change enable */
76: #define INTR_RFAULT_IE 0x0200 /* Remote fault enable */
77: #define INTR_ANEGCOMP_IE 0x0100 /* Autonegotiation complete enable */
78: #define INTR_JABBER_INT 0x0080 /* Jabber interrupt */
79: #define INTR_RXER_INT 0x0040 /* Receive error interrupt */
80: #define INTR_PRX_INT 0x0020 /* Page receive interrupt */
81: #define INTR_PDF_INT 0x0010 /* Parallel detect fault interrupt */
82: #define INTR_LPACK_INT 0x0008 /* Link partner ack. interrupt */
83: #define INTR_LSCHG_INT 0x0004 /* Link status change interrupt */
84: #define INTR_RFAULT_INT 0x0002 /* Remote fault interrupt */
85: #define INTR_ANEGCOMP_INT 0x0001 /* Autonegotiation complete interrupt */
86:
87: #define MII_TQPHY_DIAG 0x12 /* Diagnostic register */
88: #define DIAG_ANEGF 0x1000 /* Autonegotiation fail */
89: #define DIAG_DPLX 0x0800 /* Duplex (half/full) */
90: #define DIAG_RATE 0x0400 /* Rate (10/100) */
91: #define DIAG_RXPASS 0x0200 /* Receive pass */
92: #define DIAG_RXLOCK 0x0100 /* Receive lock */
93:
94: #endif /* _DEV_MII_TQPHYREG_H_ */
CVSweb